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參數資料
| 型號： | DNCM00 |
| 廠商： | Lineage Power |
| 英文描述： | 10 Mbit/s Ethernet MAC ASIC Macrocell(10 M位/秒以太網MAC ASIC宏單元) |
| 中文描述： | 10 Mbit / s的以太網MAC ASIC的宏單元（位10米/秒以太網的MAC ASIC的宏單元） |
| 文件頁數： | 1/8頁 |
| 文件大小： | 73K |
| 代理商： | DNCM00 |
Advance Data Sheet
August 1996
4
Features
I
10 Mbit/s Ethernet MAC designed to operate with
industry-standard physical layer transceivers
I
Operation in half- or full-duplex environment
I
Asynchronous reset with no clocks present
I
Interconnection with physical layers that do not
produce a continuous RXC
I
Receiver handles seven dribble bits
I
Easy simulation in
Verilog
*
or
Synopsys
synthesis
I
Compatibility with full internal scan test methodol-
ogy
*
Verilog
Inc.
Synopsys
is a registered trademark of Cadence Design Systems,
is a registered trademark of Synopsys, Inc.
Description
The DNCM00 is an 802.3 compliant MAC that is
designed to interface to industry-standard physical
layer transceivers.
The DNCM00 operates in a half- or full-duplex envi-
ronment. In half duplex, the receiver is not activated if
TXE is active to avoid buffering one’s own transmitted
packet. In full-duplex mode, the COL input from the
physical layer is ignored, and the DNCM00 can
transmit and receive data simultaneously.
All transmit and receive functions can be asynchro-
nously reset with no clocks present. For interconnec-
tion with physical layers that do not produce a
continuous RXC, the DNCM00 receiver completes a
packet reception with as few as three RX clocks after
CRS falls. The receiver will also correctly handle up
to seven dribble bits.
The DNCM00 is described in fully synthesizable
behavioral
Verilog
with 2-state table format state
machines for easy simulation in
synthesis.
Verilog
or
Synopsys
The DNCM00 has been designed to be used with a
full internal scan test methodology. There are test
inputs for controllability of all RESET signals, and the
DNCM00 can be synthesized in the Lucent Technolo-
gies libraries with flip-flop types that guarantee scan
equivalent types if scan is inserted. The DNCM00 is
approximately 10K grids in size without scan, and
approximately 12K grids in size with scan.
All control inputs to the DNCM00 are assumed to be
stable levels that remain valid for the duration of a
transmitted or received packet. They are not regis-
tered or resynchronized to a clock in the DNCM00.
DNCM00
10 Mbit/s Ethernet MAC ASIC Macrocell
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
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