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參數資料
| 型號： | DS1280 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3-Wire to Bytewide Converter Chip(3線至字節寬度（8位）轉換芯片) |
| 中文描述： | 3線，以Bytewide轉換器芯片（3線至字節寬度（8位）轉換芯片） |
| 文件頁數： | 1/11頁 |
| 文件大小： | 132K |
| 代理商： | DS1280 |
DS1280
3-Wire to Bytewide Converter Chip
DS1280
021998 1/11
FEATURES
Adapts JEDEC bytewide memory to a 3-wire serial
port
Supports 512K bytes of memory
68-pin version provides arbitration mechanisms for
dual port operation
CMOS circuitry design for battery backup and battery
operate applications
Cyclic redundancy check monitors serial data
transmission for error
Available in 44- or 80-pin quad flat pack for high den-
sity requirements
ORDERING INFORMATION
DS1280FP-XX
-80
-44
80-pin Flat Pack
44-pin Flat Pack
PIN DESCRIPTION
RST
DQ
CLK
DQE
CEB
OEB
WEB
A0B-A18B
D0B-D7B
CER
WER
OER
A0R-A18R
D0R-D7R
GND
V
CC
– Reset For Serial Port
– Data Input/Output For Serial Port
– Clock Input For Serial Port
– Serial Port Active Output
– System Bus Enable
– System Bus Read Enable
– System Bus Write Enable
– System Address Bus
– System Data Bus
– RAM Chip Enable
– RAM Write Enable
– RAM Output Enable
– RAM Address Bus
– RAM Data Bus
– Ground
– +5 Volts
PIN ASSIGNMENT
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66 65
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 40
NC
D7B
D7R
D6B
D6R
D5R
D4B
D3B
D3R
D2B
D2R
D1B
D1R
D0R
A18B
NC
NC
NC
A2B
NC
NC
NC
A3R
A3B
A4B
A5R
A5B
A6B
A7R
A7B
A8B
A9R
A9B
A10R
A10B
NC
NC
NC
A
A
A
A
A
R
C
G
V
D
C
C
W
W
O
O
A
A
A
A
A
A
A
G
V
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
121314 1617181920212223
DS1280FP-80
80-Pin Flat Pack
See Mech. Drawings
Section
24
25
26
27
28
29
30
31
32
33
4443424140393837363534
DS1280FP-44
44-Pin Flat Pack
See Mech. Drawings
Section
NC
A18R
A17R
A16R
A15R
VCC
GND
A14R
A13R
A12R
NC
OER
WER
CER
DQOE
VCC
GND
CLK
RST
A0R
A1R
A2R
N
D
D
D
D
D
D
D
D
D
N
N
A
A
A
A
A
A
A
A
A
N
DESCRIPTION
The DS1280 adds a 3-wire serial port to a bytewide stat-
ic RAM yet maintains the existing bytewide port.
Memory capacity of up to 512K bytes can be addressed
directly. Arbitration between the serial and bytewide
port is accomplished by handshaking or using predict-
able idle time as an access window. The serial port re-
quires a 6-byte protocol to set up memory transfers. Cy-
clic redundancy check circuitry is included to monitor
serial data transmission for error.
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