
AlCopyright 1995 by Dallas Semiconductor Corporation.
DS1395/DS1397
RAMified Real Time Clock
DS1395/DS1397
DD
SQW
A4
BAT
IRQ
RESET
RD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A2
A3
V
A5
V
BGND
WR
XRAM
RTC
SS
DD
SQW
A4
A5
NC
IRQ
RESET
RD
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A0
A1
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
A2
A3
V
NC
WR
XRAM
RTC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SS
V
DD
SQW
A4
A5
V
IRQ
RESET
RD
BAT
A0
A1
X2
X1
D0
D1
D2
D3
D4
D5
D6
D7
A2
A3
V
BGND
WR
XRAM
SS
A0
A1
X2
X1
D0
D1
D2
D3
D4
D5
D6
D7
V
STBY
RTC
STBY
STBY
DS1395S 28-Pin SOIC (330 mil)
DS1395 28-Pin DIP (600 mil)
DS1397 28-Pin Encapsulated Package (720 mil)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
020794 1/19
FEATURES
Ideal for EISA bus PCs
Functionally compatible with MC146818 in 32 KHz
mode
Totally nonvolatile with over 10 years of operation in
the absence of power
Self-contained subsystem includes lithium, quartz,
and support circuitry
Counts seconds, minutes, hours, day of the week,
date, month, and year with leap year compensation
Binary or BCD representations of time, calendar, and
alarm
12- or 24-hour clock with AM and PM in 12-hour mode
Daylight Savings Time option
Interfaced with software as 64 register/RAM locations
plus 4K x 8 of static RAM
– 14 bytes of clock and control registers
– 50 bytes of general and control registers
– Separate 4K x 8 nonvolatile SRAM
Programmable square wave output signal
Bus-compatible interrupt signals (IRQ)
Three interrupts are separately software-maskable
and testable:
– Time-of-day alarm once/second to once/day
– Periodic rates from 122
μ
s to 500 ms
– End-of-clock update cycle
28-pin JEDEC footprint
Available as chip (DS1395/DS1395S) or stand alone
module with embedded lithium battery and crystal
(DS1397)
ORDERING INFORMATION
DS1395
RTC Chip; 28–pin DIP
DS1395S
RTC Chip; 28–pin SOIC
DS1397
RTC Module; 28–pin DIP
PIN ASSIGNMENT