
DS2064
8K x 8 Static RAM
DS2064
022598 1/9
FEATURES
Low power CMOS design
Standby current
50 nA max at t
A
= 25
°
C V
CC
= 3.0V
100 nA max at t
A
= 25
°
C V
CC
= 5.5V
1
μ
A max at t
A
= 60
°
C V
CC
= 5.5V
Full operation for V
CC
= 4.5V to 5.5V
Data Retention Voltage = 5.5V to 2.0V
Access time equals 200 ns at 5.0V
Operating temperature range of –40
°
C to +85
°
C
Full static operation
TTL compatible inputs and outputs
Available in 28–pin DIP and 28–pin SOIC packages
Suitable for both battery operated and battery backup
applications
PIN ASSIGNMENT
V
CC
WE
CE2
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DS2064–200 28–PIN DIP (600 MIL)
DS2064S–200 28–PIN SOIC (330 MIL)
PIN DESCRIPTION
A0–A12
DQ0–DQ7
CE1, CE2
WE
OE
V
CC
GND
NC
– Address Inputs
– Data Input/Output
– Chip Enable Inputs
– Write Enable Input
– Output Enable Input
– 5V Power Supply Input
– Ground
– No Connection
DESCRIPTION
The DS2064 is a 65536–bit low power, fully static ran-
dom access memory organized as 8192 words by eight
bits using CMOS technology. The device operates from
a single power supply with a voltage input between 4.5V
and 5.5V. The chip enable inputs (CE1 and CE2) are
used for device selection and can be used in order to
achieve the minimum standby current mode, which fa-
cilitates both battery operate and battery backup appli-
cations. The device provides fast access time of 200 ns
and is most suitable for low power applications where
battery operation or battery backup for nonvolatility are
required. The DS2064 is a JEDEC–standard 8K x 8
SRAM and is pin–compatible with ROM and EPROM of
similar density.