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參數(shù)資料
| 型號： | DS2188SN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 0K |
| 描述： | IC ATTEN JTR T1/CEPT IND 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 類型： | 漂移衰減器 |
| 應(yīng)用： | T1/CEPT |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
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100600
FEATURES
Attenuates clock and data jitter present in T1
or CEPT lines
Meets
the
jitter
attenuation
templates
outlined
in
TR62411,
TR-TSY-000170,
G.735, and G.742
Only one external component required; either
a 6.176 MHz (T1) or 8.192 MHz (CEPT)
crystal
Selectable buffer size of 128 or 32 bits
Jitter attenuation is easily disabled
Single
+5V
supply;
low-power
CMOS
technology
Available in 16-pin DIP and 16-pin SOIC
(DS2188S)
Companion to the DS2186 Transmit Line
and DS2187 Receive Line Interface
PIN ASSIGNMENT
ORDERING INFORMATION
DS2188
16 Pin dip
(0C-F70C)
DS2188S
16 Pin SOIC (0-+70C)
DS2188N
16 Pin dip
(-40C-+85C)
DS2188SN
16 Pin SOIC (-40C-+85-C)
DESCRIPTION
The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an
external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all
of the latest applicable specifications including those outlined in TR 62411 (Accunet* T1.5 Service
Description and Interface Specifications, December 1990), TR-TSY-000170 (Digital Cross-Connect
System Requirements and Objectives, November 1985), and the CCITT Recommendations G.735 and
G.742. The DS2188 is compatible with the DS2180A T1/ISDN Primary Rate Transceiver and DS2181A
CEPT Transceiver and is the companion to the DS2187 T1/CEPT Receive Line Interface and DS2186
T1/CEPT Transmit Line Interface. It can also be used in conjunction with the DS2190 T1 Network
Interface Unit.
OVERVIEW
The RCLK input is fed to a 128 x 2-bit FIFO where it drives the write pointer for the positive (RPOS) and
negative (RNEG) data. The read pointer of the FIFO and RRCLK is generated by dividing the frequency
of the crystal connected to XTAL1 and XTAL2 by four. The frequency of the crystal is adjusted by a
DPLL to the long-term average frequency of RCLK. As long as the jitter present at RCLK is less than
120 unit intervals peak-to-peak (UIpp), then the FIFO buffer will be able to absorb the incoming jitter and
it will be attenuated in accordance with TR 62411 (December 1990). In this situation, the BL (Buffer
Limit) pin will remain low. Figures 1 and 2 illustrate the DS2188 Jitter Attenuator performance.
If the incoming jitter has excursions greater than 120 UIpp, then the crystal is adjusted to track the short-
term frequency variations of the incoming signal so that there is no loss of data. This adjustment is
accomplished by dividing the 4X crystal by either 3 or 4 instead of 4. When the incoming jitter is
DS2188
T1/CEPT Jitter Attenuator
www.dalsemi.com
DJA
1
16
VDD
RPOS
2
15
RRPOS
RNEG
3
14
RRNEG
RCLK
4
13
RRCLK
BDS
5
12
RST
TEST
6
11
BL
XTAL OUT
7
10
XTAL2
VSS
8
9
XTAL1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2188SN/T&R | 制造商:Maxim Integrated Products 功能描述:JITTER ATTENUATOR-SOIC-IND TRL - Tape and Reel |
| DS2188SN/T&R | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS2188SN/TRL | 功能描述:IC ATTEN JTR T1/CEPT IND 16-SOIC RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| DS2188SN+ | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS2188SN+T&R | 制造商:Maxim Integrated Products 功能描述:T1/CEPT JITTER ATTENUATOR 16SOIC W - Tape and Reel |
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