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參數資料
型號: DS2740U+T&R
廠商: Maxim Integrated
文件頁數: 9/16頁
文件大小: 304K
描述: IC CURRENT GAUGE(15BIT) 8UMAX
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 3,000
功能: 電流計(15 位)
輸入電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-uMAX
包裝: 帶卷 (TR)
DS2740
The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as
shown in Figure 8, or it can be generated in software. Additional information about the Dallas 1-Wire
CRC is available in Application Note 27, Understanding and Using Cyclic Redundancy Checks with 
Dallas Semiconductor i
Button Products.  (This  application  note  can  be  found  on  the  Maxim/Dallas 
Semiconductor website at www.maxim-ic.com.)
 
In the circuit in Figure 8, the shift register bits are initialized to 0. Then, starting with the least significant
bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,
then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value.
 
Figure 8. 1-Wire CRC GENERATION BLOCK DIAGRAM  
 
MSb
 
 
 
 
XOR
 
XOR
 
LSb
XOR
INPUT
 
 
 
 
 
 
 
HARDWARE CONFIGURATION 
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the
bus with open-drain or tri-state output drivers. The DS2740 uses an open-drain output driver as part of the
bidirectional interface circuitry shown in Figure 9. If a bidirectional pin is not available on the bus master,
separate output and input pins can be connected together.
 
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the
value of this resistor should be approximately 5k? The idle state for the 1-Wire bus is high. If, for any
reason, a bus transaction must be suspended, the bus must be left in the idle state to properly resume the
transaction later. If the bus is left low for more than 120?/SPAN>s (16?/SPAN>s for overdrive speed), slave devices on
the bus begin to interpret the low period as a reset pulse, effectively terminating the transaction.
 
The DS2740 can operate in two communication speed modes, standard and overdrive. The speed mode is
determined by the input logic level of the OVD pin with a logic 0 selecting standard Speed and a logic 1
selecting overdrive speed. The OVD pin must be at a stable logic level of 0 or 1 before initializing a
transaction with a reset pulse. All 1-Wire devices on a multinode bus must operate at the same
communication speed for proper operation. 1-Wire timing for both standard and overdrive speeds are
listed in the Electrical Characteristics: 1-Wire Interface tables.
 
9 of 16
 
 
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