- 您現在的位置：買賣IC網 > PDF目錄376977 > DS38C86A PDF資料下載
參數資料
| 型號： | DS38C86A |
| 文件頁數： | 1/10頁 |
| 文件大小： | 155K |
| 代理商： | DS38C86A |
DS38C86A
CMOS BTL 9-Bit Latching Data Transceiver
General Description
The DS38C86A is a 9-bit BTL Latching Data Transceiver de-
signed specifically for proprietary bus interfaces. The device
is implemented in CMOS technology, and delivers all of the
performance of its Bi-CMOS counterparts while consuming
less then half of the power supply current of the DS3886A.
The DS38C86A conforms to the IEEE 11941.1 (Backplane
Transceiver Logic - BTL) Standard.
The DS38C86A incorporates an edge-triggered latch in the
driver path which can be bypassed during fall-through mode
of operation and a transparent latch in the receiver path. The
DS38C86A driver output configuration is an open drain
which allows Wired-OR connection on the bus. A unique de-
sign reduces the bus loading to 3 pF typical. The driver also
has high sink current capability to comply with the bus load-
ing requirements defined within IEEE 11941.1 BTL specifica-
tion.
Backplane Transceiver Logic (BTL) is a signaling standard
that was invented and first introduced by National Semicon-
ductor, then developed by the IEEE to enhance the perfor-
mance of backplane buses. BTL transceivers feature low
output capacitance drivers to minimize bus loading, a 1V
nominal signal swing for reduced power consumption and
receivers with precision thresholds for maximum noise im-
munity. The BTL standard eliminates settling time delays that
severely limit TTL bus performance, and thus provide signifi-
cantly higher bus transfer rates. The backplane bus is in-
tended to be operated with termination resistors (selected to
match the bus impedance) connected to a 2.1V at both ends.
The low voltage is typically 1V.
The DS38C86A provides an alternative to high power Bipo-
lar and BiCMOS devices with the use of CMOS technology.
The CMOS technology enables the DS38C86A to operate at
50% of the I
required by the Bi-CMOS DS3886A. This can
have a major impact on system power consumption. For ex-
ample, if a backplane is 128 bits wide, 16 devices (9 bits
each) required per card. Also assume the backplane is one
rack with 20 slots. Power dissipation savings for this applica-
tion is calculated by the following equation:
P = I
CC
-savings x Power supply voltage x number of devices
P = 32 mA x 5.5V x 320 = 56 Watts
The power dissipation savings may increase even more
when; the system bus is wider than 128 bits, there are mul-
tiple racks in the system, or if the system includes a hot
backup. This may double the power dissipation savings.
Separate ground pins are provided for each BTL output mini-
mize induced ground noise during simultaneous switching.
The unique driver circuitry provides a maximum slew rate of
0.9V/ns which allows controlled rise and fall times to reduce
noise coupling to adjacent lines.
The transceiver’s high impedance control and driver inputs
are fully TTL compatible.
The receiver is a high speed comparator that utilizes a Band-
gap reference for precision threshold control allowing maxi-
mum immunity to the BTL 1V signaling level.
Separate QV
and QGND pins are provided to minimize
the effects of high current switching noise. The receiver out-
put is TRI-STATE
and fully TTL compatible.
The DS38C86A supports live insertion as defined in IEEE
896.2 through the LI (Live Insertion) pin. To implement live
insertion the LI pin should be connected to the live insertion
power connector. If this function is not supported, the LI pin
must be tied to the V
pin. The DS38C86A also provides
glitch free power up/down protection during power sequenc-
ing.
The DS38C86A has two types of power connections in addi-
tion to the LI pin. They are the Logic V
(V
CC
) and the Quiet
V
(QV
). There are two Logic V
pins on the
DS38C86A that provide the supply voltage for the logic and
control circuitry. Multiple connections are provided to reduce
the effects of package inductance and thereby minimize
switching noise. A voltage delta between V
and QV
CC
should never exceed
±
0.5V because of ESD circuitry.
When CD (Chip Disable) is high, An is in high impedance
state and Bn is high. To transmit data (An to Bn), the T/R sig-
nal is high.
When RBYP is high, the positive edge triggered flip-flop is in
the transparent mode. When RBYP is low, the positive edge
of the ACLK signal clocks the data.
In addition, the ESD circuitry between the V
pins and all
other pins except for BTL I/O’s and LI pins requires that any
voltage on these pins should not exceed the voltage on V
CC
+0.5V.
There are three different types of ground pins on the
DS38C86A;
the
logic
ground
(B0GND–B8GND) and the Bandgap reference ground
(QGND). All of these ground reference pins are isolated
within the chip to minimize the effects of high current switch-
ing transients. For optimum performance the QGND should
be returned to the connector through a quiet channel that
does not carry transient switching current. The GND and
B0GND–B8GND should be connected to the nearest back-
plane ground pin with the shortest possible path.
Since many different grounding schemes could be imple-
mented and ESD circuitry exists on the DS38C86A, it is im-
portant to note that any voltage between ground pins,
QGND, GND or B0GND–B8GND should not exceed
±
0.5V
including power up/down sequencing.
The DS38C86A is offered in a 48-pin 7 x 7 space saving
PQFP package.
(GND),
BTL
grounds
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
July 1998
D
1999 National Semiconductor Corporation
DS012623
www.national.com
相關PDF資料 |
PDF描述 |
|---|---|
| DS38C86AVB | 9-Bit Bus Transceiver |
| DS3903 | Triple 128-Position Nonvolatile Digital Potentiometer |
| DS3930 | Hex Nonvolatile Potentiometer with I/O and Memory |
| DS3930E | Hex Nonvolatile Potentiometer with I/O and Memory |
| DS3930 | RELIABILITY REPORT FOR DS3930, REV A1 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS38C86AVB | 制造商:Texas Instruments 功能描述: |
| DS38EP100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:1 to 5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS38EP100EVK | 功能描述:BOARD EVAL FOR DS38EP100 RoHS:否 類別:編程器，開發系統 >> 評估演示板和套件 系列:PowerWise® 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| DS38EP100-EVK | 功能描述:其他開發工具 DS38EP100 POWER SAVER EVAL KIT RoHS:否 制造商:Parallax 產品:ELEV-8 Hex Upgrade Kits 類型:Robotics 工具用于評估:ELEV-8 Quadcopter 工作電源電壓: |
| DS38EP100EVKH | 功能描述:BOARD EVAL FOR DS38EP100 HDMI RoHS:否 類別:編程器，開發系統 >> 評估演示板和套件 系列:PowerWise® 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
發布緊急采購，3分鐘左右您將得到回復。