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參數資料
| 型號： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數字信號處理器 |
| 文件頁數： | 1/154頁 |
| 文件大小： | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
1 Features
I
Optimized for digital cellular applications with a bit manip-
ulation unit for higher coding efficiency.
I
On-chip, programmable, PLL clock synthesizer.
I
14 ns and 11 ns instruction cycle times at 5 V, 10 ns in-
struction cycle time at 3.0 V, and 20 ns and 12.5 ns in-
struction cycle times at 2.7 V, respectively.
I
Mask-programmable memory map option: The
DSP1627x36 features 36 Kwords on-chip ROM. The
DSP1627x32 features 32 Kwords on-chip ROM and ac-
cess to 16 Kwords external ROM in the same map. Both
feature 6 Kwords on-chip, dual-port RAM and a secure
option for on-chip ROM.
I
Low power consumption:
— <5.5 mW/MIPS typical at 5 V.
— <1.5 mW/MIPS typical at 2.7 V.
I
Flexible power management modes:
— Standard sleep: 0.5 mW/MIPS at 5 V.
0.12 mW/MIPS at 2.7 V.
— Sleep with slow internal clock: 1.4 mW at 5 V.
0.4 mW at 2.7 V.
— Hardware STOP (pin halts DSP): <20
μ
A.
I
Mask-programmable clock options: crystal oscillator,
small signal, and CMOS.
I
Low-profile TQFP package (1.5 mm) available.
I
Sequenced accesses to X and Y external memory.
I
Object code compatible with the DSP1617.
I
Single-cycle squaring.
I
16 x 16-bit multiplication and 36-bit accumulation in one
instruction cycle.
I
Instruction cache for high-speed, program-efficient, zero-
overhead looping.
I
Dual 25 Mbits/s serial I/O ports with multiprocessor capa-
bility—16-bit data channel, 8-bit protocol channel.
I
8-bit parallel host interface:
— Supports 8- or 16-bit transfers.
— Motorola
*
or Intel
compatible.
I
8-bit control I/O interface.
I
256 memory-mapped I/O ports.
I
IEEE
P1149.1 test port (JTAG boundary scan).
I
Full-speed in-circuit emulation hardware development
system on-chip.
I
Supported by DSP1627 software and hardware develop-
ment tools.
2 Description
The DSP1627 is Lucent Technologies Microelectronics
Group first digital signal processor offering 100 MIPS oper-
ation at 3.0 V and 80 MIPS operation at 2.7 V with a reduc-
tion in power consumption. Designed specifically for
applications requiring low power dissipation in digital cellu-
lar systems, the DSP1627 is a signal-coding device that can
be programmed to perform a wide variety of fixed-point sig-
nal processing functions. The device is based on the
DSP1600 core with a bit manipulation unit for enhanced sig-
nal coding efficiency. The DSP1627 includes a mix of pe-
ripherals specifically intended to support processing-
intensive but cost-sensitive applications in the area of digital
wireless communications.
The DSP1627x36 contains 36 Kwords of internal ROM
(IROM), but it doesn’t support the use of IROM and external
ROM (EROM) in the same memory map. The DSP1627x32
supports the use of 32 Kwords of IROM with 16 Kwords of
EROM in the same map. Both devices contain 6 Kwords of
dual-port RAM (DPRAM), which allows simultaneous ac-
cess to two RAM locations in a single instruction cycle.
The DSP1627 is object code compatible with the DSP1617,
while providing more memory and architectural enhance-
ments including an on-chip clock synthesizer and an 8-bit
parallel host interface for hardware flexibility.
The DSP1627 supports 2.7 V, 3.0 V, and 5 V operation and
flexible power management modes required for portable
cellular terminals. Several control mechanisms achieve low-
power operation, including a STOP pin for placing the DSP
into a fully static, halted state and a programmable power
control register used to power down unused on-chip I/O
units. These power management modes allow for trade-offs
between power reduction and wake-up latency require-
ments. During system standby, power consumption is re-
duced to less than 20
μ
A.
The on-chip clock synthesizer can be driven by an external
clock whose frequency is a fraction of the instruction rate.
The device is packaged in a 100-pin BQFP or a 100-pin
TQFP and is available with 14 ns and 11 ns instruction cycle
times at 5 V, 10 ns instruction cycle times at 3.0 V, and
20 ns and 12.5 ns instruction cycle times at 2.7 V, respec-
tively.
*
Intelis a registered trademark of Intel Corp.
IEEE is a registered trademark of The Institute of Electrical
and Electronics Engineers, Inc.
Motorolais a registered trademark of Motorola, Inc.
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| DSP1627F32K10IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| DSP1627F32K11IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
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