xc4010xl-09pq100c特點:
     為了提高性能，xc4010xl - 09pq100c有一個為用戶誰想要小于0.01％的初始error.for噪聲應用，一個外部電容外部裝飾選項可以減少引腳之間的噪聲和地面引腳連接。
xc4010xl-09pq100c(絕對)最大額定值:
     數據寫入在寫或讀寫周期。根據不同的運作模式，中科院或w頻閃燈數據落入芯片上的數據鎖存邊緣。在一個早期寫周期，w是前低帶來的數據是中國科學院和選通通過與中科院在體制和保持參照這個信號倍。在延遲寫入或讀寫周期，中科院已經很低，數據選通是由w與建立和保持參照這個信號倍。
xc4010xl-09pq100c引腳說明:     8位6502兼容cpu運行在6mhz的。地址總線為16位和數據總線是8位。非屏蔽中斷（/海里）的6502修改為屏蔽，并作為具有較高優先權的有int0定義。中斷請求（/ irq）的定義為6502的int1的低優先級。
xc4010xl-09pq100c features:
for enhanced performance, the xc4010xl-09pq100c has an external trim option for users who want less than 0.01% initial error.for ultra low noise applications, an external capacitor can be attached between the noise reduction pin and the ground pin.
xc4010xl-09pq100c(absolute) maximum ratings:
data is written during a write or read-write cycle. depending on the mode of operation, the falling edge of cas or w strobes data into the on-chip data latch. in an early-write cycle, w is brought low prior to cas and the data is strobed in by cas with setup and hold times referenced to this signal. in a delayed-write or read-write cycle, cas is already low and the data is strobed in by w with setup and hold times referenced to this signal.
xc4010xl-09pq100c pinout: 8-bit 6502 compatible cpu operates at 6mhz. address bus is 16-bit and data bus is 8-bit. the non-maskable interrupt (/nmi) of 6502 is modified to be maskable and is defined as int0 with higher priority. the interrupt request (/irq) of 6502 is defined as int1 with lower priority