1. general description
the 74hc373; 74hct373 is a high-speed si-gate cmos device and is pin compatible
with low-power schottky ttl. it is specified in compliance with jedec standard no. 7a.
the 74hc373; 74hct373 is an octal d-type transparent latch featuring separate d-type
inputs for each latch and 3-state outputs for bus oriented applications. a latch enable (le)
input and an output enable (oe) input are common to all latches.
the 74hc373; hct373 consists of eight d-type transparent latches with 3-state true
outputs. when le is high, data at the dn inputs enters the latches. in this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
d input changes.
when le is low the latches store the information that was present at the d inputs a
set-up time preceding the high-to-low transition of le. when oe is low, the contents
of the 8 latches are available at the outputs. when oe is high, the outputs go to the highimpedance
off-state. operation of the oe input does not affect the state of the latches.
the 74hc373; 74hct373 is functionally identical to:
• 74hc533; 74hct533: but inverted outputs
• 74hc563; 74hct563: but inverted outputs and different pin arrangement
• 74hc573; 74hct573: but different pin arrangement

2. features
3-state non-inverting outputs for bus oriented applications
common 3-state output enable input
functionally identical to the 74hc563; 74hct563, 74hc573; 74hct573 and
74hc533; 74hct533
esd protection:
hbm eia/jesd22-a114-c exceeds 2 000 v
mm eia/jesd22-a115-a exceeds 200 v
specified from -40 °c to +85 °c and from -40 °c to +125 °c