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參數資料
| 型號： | E5530H-ZZZ-S8 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 英文描述： | 128-Bit IDIC for Radio Frequency Identification |
| 中文描述： | 128位投資業務的無線電頻率識別 |
| 文件頁數： | 1/5頁 |
| 文件大?。?/td> | 72K |
| 代理商： | E5530H-ZZZ-S8 |
e5530
Rev. A3, 17-Sep-98
1 (5)
128-Bit IDIC for Radio Frequency Identification
Description
The e5530 is part of a closed coupled identification
system. It receives power from an RF transmitter which
is coupled inductively to the IDIC. The frequency is
typically 100 to 450 kHz. Receiving RF, the IDIC
responds with a data stream by damping the incoming RF
via an internal load. This damping-in-turn can be detected
by the interrogator. The identifying data are stored in a
128 bit PROM on the e5530, realized as an array of laser-
programmable fuses. The logic block diagram for the
e5530 is shown in figure 2. The data are output bit-
serially as a code of length 128, 96, 64 or 32 bits. The
chips are factory-programmed with a unique code.
Features
D Low power, low voltage CMOS
D Rectifier, voltage limiter, clock extraction
on-chip (no battery)
D Small size
D Factory laser programmable ROM
D Operating temperature range –40 to +125°C
D Radio Frequency (RF): 100 to 450 kHz
D Transmission options
Code length: 128, 96, 64, 32 bits
Bitrate [bit/s]:
RF/8,RF/16, RF/32, RF/40,
RF/50, RF/64, RF/80, RF/100,
RF/128, RF/256
Modulation:
FSK, PSK, BIPH, Manchester
BIPH-FSK
Application
RF transmitter
and
interrogator
e5530
RF
95 10318
IDIC
Figure 1. Application
R7
R6
R5
R4
R3
R2
R1
R0
Row
decoder
C15
C14
C13
C12
C1
1
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
Column decoder
A2
A1
A0
A6
A5
A4
A3
Counter
Modulator
FSK
PSK
BIPH
Manchester
Bitrate
Data
Load
Clock
extractor
Rectifier
Mod
Clk
Analog front end
Coil
VDD
VSS
128 bit PROM
95 10155
Figure 2. Block diagram
IDIC stands for IDentification Integrated Circuit and is a trademark of TEMIC.
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