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參數資料
| 型號： | E629-EDGE629 |
| 英文描述： | 1 GHz Timing Deskew and Quad Fanout Element |
| 中文描述： | 1 GHz的定時偏移校正和四扇出元素 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 137K |
| 代理商： | E629-EDGE629 |
HIGH-PERFORMANCE PRODUCTS – ATE
1
www .semtech.com
Edge629
1 GHz Timing Deskew and
Quad Fanout Element
Description
Featur es
Functional Block Diagram
Applications
Revision 1 / Febr uar y 13, 2002
The Edge629 is a monolithic timing delay and signal
fanout solution manufactured in a high-performance
bipolar process. In Automatic Test Equipment (ATE)
applications, the Edge629 buffers, distributes, and aligns
timing signals across multiple channels (typically found
inside Memory Test Systems). It is also suitable for per
pin deskew in Logic Testers.
The Edge629 supports:
Minimum pulse width = 330 ps with Falling
Edge Adjust disabled, 500 ps with Falling
Edge Adjust enabled
Net usable delay span
≥ 4.0 ns
Falling Edge Adjust
±250 ps
On Board DACs to generate 5 ps minimum
resolution.
With a maximum operating frequency of 1 GHz, the
Edge629 is optimized for extremely high speed, high
accuracy testers, particularly those aimed to test
RAMBUS memory devices.
The Edge629 solves several difficult problems
associated with aligning multiple timing signals because
it can:
delay very narrow pulses over a long
timing span
adjust the falling edge independently from the overall
propagation delay
maintain extreme timing accuracy for very narrow
(sub-ns) pulses
maintain tight timing accuracy over changes in
frequency, duty cycle, and pattern.
Fmax
≥ 1 GHz
Independent Falling Edge Adjust
Small Footprint (10 mm x 10 mm)
Excellent Timing Accuracy
Very Stable Timing Delays
5 ps Minimum Resolution
ECL, CMOS Compatible Inputs
Memory Test Equipment
–
Data Fanout
–
Channel Deskew
Logic Testers
–
Per Pin Deskew
Clock / Signal Fanout
T
T–
T
Coarse
Fine
OUT0 / OUT0*
IN0 / IN0*
IN / IN*
Coarse
Fine
OUT1 / OUT1*
IN1/ IN1*
Coarse
Fine
OUT2 / OUT2*
IN2 / IN2*
Coarse
Fine
OUT3 / OUT3*
IN3 / IN3*
SEL / SEL*
T
T–
TARGET
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