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參數(shù)資料
| 型號： | EBD51RC4AKFA-7A |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512MB Registered DDR SDRAM DIMM (64M words X 72 bits, 1 Rank) |
| 中文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大小： | 198K |
| 代理商： | EBD51RC4AKFA-7A |
Document No. E0377E20 (Ver. 2.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2003-2004
DATA SHEET
512MB Registered DDR SDRAM DIMM
EBD51RC4AKFA
(64M words
×
72 bits, 1 Rank)
Description
The EBD51RC4AKFA is a 64M words
×
72 bits, 1 rank
Double Data Rate (DDR) SDRAM Module, mounting 18
pieces of DDR SDRAM sealed in TSOP package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2-bit prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing surface mount technology. Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8
μ
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
1 piece of PLL clock driver, 2 pieces of register
drivers and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBD51RC4AKFA-7B | Circular Connector; No. of Contacts:26; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-26 RoHS Compliant: No |
| EBD51RC4AKFA-7B-E | JT 55C 55#22D PIN PLUG |
| EBD51RC4AKFA-E | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No |
| EBD52UC8AKDA-6B | 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5 | JT 12C 8#20 4#16 SKT PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBD51RC4AKFA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Registered DDR SDRAM DIMM (64M words x 72 bits, 1 Rank) |
| EBD51RC4AKFA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Registered DDR SDRAM DIMM (64M words X 72 bits, 1 Rank) |
| EBD51RC4AKFA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Registered DDR SDRAM DIMM (64M words x 72 bits, 1 Rank) |
| EBD51RC4AKFA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Registered DDR SDRAM DIMM (64M words x 72 bits, 1 Rank) |
| EBD51RD8ABFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Registered DDR SDRAM DIMM |
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