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參數資料
| 型號： | EDI416S4030A12SI |
| 英文描述： | 1Mx 16 Bits x 4 Banks Synchronous DRAM(83MHz,1M x 16 位 x 4 組同步動態RAM) |
| 中文描述： | 1Mx 16位× 4個銀行同步DRAM（83MHz，100萬× 16位× 4個組同步動態RAM）的 |
| 文件頁數： | 1/26頁 |
| 文件大小： | 353K |
| 代理商： | EDI416S4030A12SI |
EDI416S4030A
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
FIG. 1
PIN DESCRIPTION
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CE
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
TERMINAL
CONNECTIONS
(T
OP
VEIW)
June 2000 Rev. 0
ECO# 12862
DESCRIPTION
The EDI416S4030A is 67,108,864 bits of synchronous high data
rate DRAM organized as 4 x 1,048,576 words x 16 bits. Synchronous
design allows precise cycle control with the use of system clock,
I/O transactions are possible on every clock cycle. Range of
operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
Available in a 54 pin TSOP type II package the EDI416S4030A is
tested over the industrial temp range (-40
°C to +85°C) providing
a solution for rugged main memory applications.
1M x 16 Bits x 4 Banks Synchronous DRAM
FEATURES
s Single 3.3V power supply
s Fully Synchronous to positive Clock Edge
s Clock Frequency = 100, 83MHz
s SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz)
s Burst Operation
Sequential or Interleave
Burst length = programmable 1,2,4,8 or full page
Burst Read and Write
Multiple Burst Read and Single Write
s DATA Mask Control per byte
s Auto Refresh (CBR) and Self Refresh
4096 refresh cycles across 64ms
s Automatic and Controlled Precharge Commands
s Suspend Mode and Power Down Mode
s Industrial Temperature Range
A0-11
Address Inputs
BA0, BA1
Bank Select Addresses
CE
Chip Select
WE
Write Enable
CLK
Clock Input
CKE
Clock Enable
DQ0-15
Data Input/Output
L(U)DQM
Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
VDD
Power (3.3V)
VDDQ
Data Output Power
VSS
Ground
VSSQ
Data Output Ground
NC
No Connection
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