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參數資料
| 型號： | EDI88128C70NC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 70 ns, CDSO32 |
| 封裝： | CERAMIC, SOJ-32 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 386K |
| 代理商： | EDI88128C70NC |
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI88128C
April 2005
Rev. 17
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
128Kx8 MONOLITHIC SRAM, SMD 5962-89598
FEATURES
Access Times of 70, 85, 100ns
Available with Single Chip Selects (EDI88128) or
Dual Chip Selects (EDI88130)
2V Data Retention (LP Versions)
CS# and OE# Functions for Bus Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 128Kx8
Industrial, Military and Commercial Temperature
Ranges
Thru-hole and Surface Mount Packages JEDEC
Pinout
32 pin Ceramic DIP, 0.6 mils wide (Package 9)
32 lead Ceramic SOJ (Package 140)
Single +5V (±10%) Supply Operation
PIN DESCRIPTION
I/O0-7
A0-16
WE#
CS1#, CS2
OE#
V
CC
V
SS
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
BLOCK DIAGRAM
FIGURE 1 – PIN CONFIGURATION
The EDI88128C is a high speed, high performance,
Monolithic CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an
additional chip select line (CS2) which will automatically
power down the device when proper logic levels are
applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in
memory banking where large multiple pages of memory
are required.
The EDI88128C and the EDI88130C have eight bi-
directional input-output lines to provide simultaneous
access to all bits in a word. An automatic power down
feature permits the on-chip circuitry to enter a very low
standby mode and be brought back into operation at a
speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer
a 2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
32 DIP
32 SOJ
Top View
* Pin 30 is NC for 88128 or CS2 for 88130.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
A15
NC/CS2*
WE#
A13
A8
A9
A11
OE#
A10
CS1#
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
I/O
I/O1
I/O2
V
SS
WE#
CS1#
CS2
OE#
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| EDI88128LPS35MI | 128K X 8 STANDARD SRAM, 35 ns, PDSO32 |
| EDI88128LPS25MI | 128K X 8 STANDARD SRAM, 25 ns, PDSO32 |
| EDI88130CS17TI | 128K X 8 STANDARD SRAM, 17 ns, CDIP32 |
| EDI88130CS25NI | 128K X 8 STANDARD SRAM, 25 ns, CDSO32 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EDI88128C70NI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128KX8 MONOLITHIC SRAM, SMD 5962-89598 |
| EDI88128C70NM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128KX8 MONOLITHIC SRAM, SMD 5962-89598 |
| EDI88128C70ZB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88128C70ZC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88128C70ZI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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