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參數(shù)資料
| 型號(hào)： | EFM32-TG108F32-SK |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 39/136頁 |
| 文件大小： | 0K |
| 描述： | IC MICRO KIT GECKO 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Tiny Gecko |
| 套件類型： | 微控制器 |
| 值： | 2 件 - 閃存 - 32KB |
| 包裝： | 紙板盒 |
| 安裝類型： | 表面貼裝 |
| 包括封裝： | 24-QFN |
| 工具箱內(nèi)容： | (2) 914-1032-2-ND - MCU 32BIT 32KB FLASH 24-QFN |
| 其它名稱： | 914-1025 |
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
133
www.energymicro.com
List of Tables
1.1. Cortex-M3 configuration in EFM32 series .................................................................................................... 5
2.1. Summary of processor mode, execution privilege level, and stack use options .................................................... 6
2.2. Core register set summary ....................................................................................................................... 7
2.3. PSR register combinations ....................................................................................................................... 9
2.4. APSR bit assignments ............................................................................................................................. 9
2.5. IPSR bit assignments ............................................................................................................................ 10
2.6. EPSR bit assignments ........................................................................................................................... 10
2.7. PRIMASK register bit assignments ........................................................................................................... 11
2.8. FAULTMASK register bit assignments ....................................................................................................... 12
2.9. BASEPRI register bit assignments ............................................................................................................ 12
2.10. CONTROL register bit assignments ........................................................................................................ 13
2.11. Memory access behavior ...................................................................................................................... 16
2.12. SRAM memory bit-banding regions ......................................................................................................... 18
2.13. Peripheral memory bit-banding regions .................................................................................................... 18
2.14. C compiler intrinsic functions for exclusive access instructions ..................................................................... 21
2.15. Properties of the different exception types ................................................................................................ 23
2.16. Exception return behavior ..................................................................................................................... 28
2.17. Faults ................................................................................................................................................ 28
2.18. Fault status and fault address registers ................................................................................................... 30
3.1. Cortex-M3 instructions ........................................................................................................................... 33
3.2. CMSIS intrinsic functions to generate some Cortex-M3 instructions ................................................................ 37
3.3. CMSIS intrinsic functions to access the special registers .............................................................................. 37
3.4. Condition code suffixes .......................................................................................................................... 44
3.5. Memory access instructions .................................................................................................................... 45
3.6. Offset ranges ...................................................................................................................................... 48
3.7. Offset ranges ....................................................................................................................................... 51
3.8. Data processing instructions .................................................................................................................... 56
3.9. Multiply and divide instructions ................................................................................................................ 66
3.10. Packing and unpacking instructions ........................................................................................................ 71
3.11. Branch and control instructions .............................................................................................................. 73
3.12. Branch ranges .................................................................................................................................... 74
3.13. Miscellaneous instructions ..................................................................................................................... 79
4.1. Core peripheral register regions ............................................................................................................... 88
4.2. NVIC register summary ......................................................................................................................... 88
4.3. Mapping of interrupts to the interrupt variables ........................................................................................... 89
4.4. ISER bit assignments ............................................................................................................................ 90
4.5. ICER bit assignments ............................................................................................................................ 90
4.6. ISPR bit assignments ............................................................................................................................ 91
4.7. ICPR bit assignments ............................................................................................................................ 91
4.8. IABR bit assignments ............................................................................................................................ 92
4.9. IPR bit assignments .............................................................................................................................. 92
4.10. STIR bit assignments ........................................................................................................................... 93
4.11. CMSIS functions for NVIC control ........................................................................................................... 94
4.12. Summary of the system control block registers ........................................................................................ 94
4.13. ACTLR bit assignments ........................................................................................................................ 95
4.14. CPUID register bit assignments ............................................................................................................ 96
4.15. ICSR bit assignments ........................................................................................................................... 97
4.16. VTOR bit assignments ........................................................................................................................ 99
4.17. AIRCR bit assignments ........................................................................................................................ 99
4.18. Priority grouping ................................................................................................................................ 100
4.19. SCR bit assignments ......................................................................................................................... 100
4.20. CCR bit assignments ........................................................................................................................ 101
4.21. System fault handler priority fields ........................................................................................................ 102
4.22. SHPR1 register bit assignments .......................................................................................................... 103
4.23. SHPR2 register bit assignments .......................................................................................................... 103
4.24. SHPR3 register bit assignments .......................................................................................................... 103
4.25. SHCSR bit assignments ...................................................................................................................... 104
4.26. MMFSR bit assignments ..................................................................................................................... 106
4.27. BFSR bit assignments ........................................................................................................................ 107
4.28. UFSR bit assignments ........................................................................................................................ 108
4.29. HFSR bit assignments ........................................................................................................................ 109
4.30. MMFAR bit assignments ..................................................................................................................... 110
4.31. BFAR bit assignments ........................................................................................................................ 110
4.32. System timer registers summary ........................................................................................................... 111
4.33. SysTick CTRL register bit assignments .................................................................................................. 111
4.34. LOAD register bit assignments ............................................................................................................. 112
4.35. VAL register bit assignments ............................................................................................................... 112
4.36. CALIB register bit assignments ............................................................................................................. 113
4.37. Memory attributes summary ................................................................................................................. 114
4.38. MPU registers summary ...................................................................................................................... 114
4.39. TYPE register bit assignments ............................................................................................................. 115
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EFM32TG108F32-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 24QFN |
| EFM32TG108F4 | 功能描述:ARM微控制器 - MCU 4KB Flash 1KB RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| EFM32TG108F4-QFN24 | 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 4KB FLASH 24QFN |
| EFM32TG108F4-QFN24T | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays |
| EFM32TG108F4-QFN24-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 4KB FLASH 24QFN |
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