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參數資料
| 型號： | EL32D1EEA1K-80.800M |
| 廠商： | ECLIPTEK CORP |
| 元件分類： | XO, clock |
| 英文描述： | VCXO, CLOCK, 80.8 MHz, LVDS OUTPUT |
| 封裝： | ROHS COMPLIANT, CERAMIC, SMD, 6 PIN |
| 文件頁數： | 1/2頁 |
| 文件大小： | 113K |
| 代理商： | EL32D1EEA1K-80.800M |
MANUFACTURER
CATEGORY
SERIES
PACKAGE
VOLTAGE
CLASS
REV
.DATE
ECLIPTEK CORP.
OSCILLATOR
EL32D1
CERAMIC
3.3V
OS3Z
10/07
EL32D1 Series
OSCILLATOR
EL32D1
ELECTRICAL SPECIFICATIONS
800-ECLIPTEK www.ecliptek.com for latest revision
Specifications subject to change without notice.
RoHS Compliant (Pb-Free)
LVDS Output Oscillators
3.3V supply voltage
Ceramic 6-pad SMD Package
Stability to ±25ppm
Tri-State Output
Complementary Output
Available on Tape and Reel
H
2.0
L
7.0
W
5.0
0°C to 70°C
-40°C to 85°C
-55°C to 125°C
3.3V
DC ±5%
247mV Minimum, 355mV Typical, 454mV Maximum
80mA Maximum
±50ppm or ±25ppm Maximum
1.43V
DC Typical, 1.6VDC Maximum
1.1V
DC Typical, 0.9VDC Minimum
-50mV Minimum, +50mV Maximum
1.125V Minimum, 1.20V Typical, 1.375V Maximum
1 nSeconds Maximum
50 ±10(%)
50 ±5(%)
25mV Maximum
100 Ohms and 10pF
1.65V
DC ±1.65VDC
0.0V
DC to VCC +0.5VDC
±75ppm Minimum
20%, 15%, or 10% Maximum
Positive Transfer Characteristic
10kHz Minimum
50kOhms Typical
-55dBc/Hz
-90dBc/Hz
-120dBc/Hz
-140dBc/Hz
-145dBc/Hz
-148dBc/Hz
Tri-State Enable High / Complementary Output
Enables Output
Disables Outputs: High Impedance
0.4pSec Typical, 1 pSec Maximum
4pSec Typical, 5pSec Maximum
3pSec Typical, 5pSec Maximum
4pSec Typical, 10pSec Maximum
27pSec Typical, 40pSec Maximum
10mSec Maximum
Frequency Range
Operating Temperature Range
Storage Temperature Range
Supply Voltage (V
CC)
Differential Output Voltage (V
OD)
Input Current
Frequency Tolerance / Stability
Output Voltage Logic High (V
OH)
Output Voltage Logic Low (V
OL)
V
DD Magnitude Change (DVOD)
Offset Voltage (V
OS)
Rise Time / Fall Time
Duty Cycle
Offset Voltage Magnitude Change (
DVOS)
Load Drive Capability
Control Voltage (V
C)
Control Voltage Range (V
CR)
Frequency Deviation
Linearity
Transfer Function
Modulation Bandwidth (MBW)
Input Impedance (Z
I)
Typical Phase Noise (Fo = 155.520MHz)
Logic Control/Additional Output
Tri-State Input Voltage
RMS Phase Jitter
Accumulated Period Jitter (t
acc)
Period Jitter (t
rj)
Period Jitter (t
rms)
Period Jitter (t
dj)
Period Jitter (t
p-p)
Start Up Time
Inclusive of all conditions: Calibration Tolerance at 25°C,
Frequency Stability over the Operating Temperature Range,
Supply Voltage Change, Output Load Change, 1st Year Aging,
Shock, and Vibration
20% to 80% of waveform
at 50% of waveform
Between Output and Complementary Output
Test Conditions for Frequency Deviation
Inclusive of Operating Temperature Range, Supply
Voltage Change, and Output Load Change
Measured at -3dB with Contol Voltage of +1.65V
DC
at 10Hz Offset
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
at 1MHz Offset
V
IH of 70% of VCC Minimum
No Connection
V
IL of 30% of VCC Maximum
FJ = 12kHz to 20MHz
Sigma of Total Jitter Distribution
Sigma of Random Jitter
Sigma of Total Jitter Distribution
Deterministic Jitter
Peak to Peak of Jitter Distribution
61.440MHz, 76.800MHz, 80.000MHz, 125.000MHz, 128.000MHz, 155.520MHz, 156.250MHz, 161.1328MHz,
167.3315MHz
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