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參數資料
型號: EP20K100ETC144-3ES
英文描述: 128-Tap DCP, 16kbit EEPROM, and I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 8-DFN
中文描述: FPGA的
文件頁數: 1/114頁
文件大小: 1623K
代理商: EP20K100ETC144-3ES
Altera Corporation
1
APEX 20K
Programmable Logic
Device Family
May 2001, ver. 3.7
Data Sheet
A-DS-APEX20K-03.7
Features...
s
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
–MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
LUT logic used for register-intensive functions
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
ESB implementation of product-term logic used for
combinatorial-intensive functions
s
High density
30,000 to 1.5 million typical gates (see Tables 1 and 2)
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
Up to 3,456 product-term-based macrocells
Table 1. APEX 20K Device Features
Feature
EP20K30E
EP20K60E
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
Maximum
system
gates
113,000
162,000
263,000
404,000
526,000
Typical
gates
30,000
60,000
100,000
160,000
200,000
LEs
1,200
2,560
4,160
6,400
8,320
ESBs
12
16
26
40
52
Maximum
RAM bits
24,576
32,768
53,248
81,920
106,496
Maximum
macrocells
192
256
416
640
832
Maximum
user I/O
pins
128
196
252
246
316
382
376
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相關代理商/技術參數
參數描述
EP20K100ETI144-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100ETI144-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100ETI144-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100FC324-1 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100FC324-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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