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參數(shù)資料
| 型號： | EP9430-250 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Single Digitally Controlled (XDCP™) Potentiometer; Temperature Range: -40°C to 85°C; Package: 14-TSSOP |
| 中文描述： | 延遲線|定額絲錐| 1線| 1 -技術(shù)咨詢|混合|雙酯| 14PIN |塑料 |
| 文件頁數(shù)： | 1/1頁 |
| 文件大小： | 12K |
| 代理商： | EP9430-250 |
14 Pin DIP Single Output TTL Compatible Active Delay Lines
TIME DELAYS
PART
TIME DELAYS
(nS)
NUMBER
(nS)
±5% or ±2 nS
5
EP9430-5
23
6
EP9430-6
24
7
EP9430-7
25
8
EP9430-8
30
9
EP9430-9
35
10
EP9430-10
40
11
EP9430-11
45
12
EP9430-12
50
13
EP9430-13
55
14
EP9430-14
60
15
EP9430-15
65
16
EP9430-16
70
17
EP9430-17
75
18
EP9430-18
80
19
EP9430-19
85
20
EP9430-20
90
21
EP9430-21
95
22
EP9430-22
100
PART
TIME DELAYS
PART
NUMBER
(nS)
NUMBER
±5% or ±2 nS
EP9430-23
125
EP9430-125
EP9430-24
150
EP9430-150
EP9430-25
175
EP9430-175
EP9430-30
200
EP9430-200
EP9430-35
225
EP9430-225
EP9430-40
250
EP9430-250
EP9430-45
275
EP9430-275
EP9430-50
300
EP9430-300
EP9430-55
350
EP9430-350
EP9430-60
400
EP9430-400
EP9430-65
500
EP9430-500
EP9430-70
600
EP9430-600
EP9430-75
700
EP9430-700
EP9430-80
800
EP9430-800
EP9430-85
900
EP9430-900
EP9430-90
1000
EP9430-1000
EP9430-95
EP9430-100
Whichever is greater.
Delay Times referenced from input to leading edges at 25°C, 5.0V, with no load.
Package Dimensions
EIN
Pulse Input Voltage
3.2
Volts
PW
Pulse Width % of Total Delay
110
%
TRI
Pulse Rise Time (0.75 - 2.4 Volts)
2.0
nS
PRR
Pulse Repetition Rate @ Td
≤ 200 nS
1.0
MHz
Pulse Repetition Rate @ Td > 200 nS
100
KHz
VCC
Supply Voltage
5.0
Volts
Input Pulse Test Conditions @ 25° C
Unit
VOH
High-Level Output Voltage
VCC= min. VIL= max. IOH = max 2.7
V
VOL
Low-Level Output Voltage
VCC= min. VIH = min. IOL= max
0.5
V
VIK
Input Clamp Voltage
VCC= min. II = IIK
-1.2
V
IIH
High-Level Input Current
VCC= max. VIN = 2.7V
50
A
VCC= max. VIN = 5.25V
1.0
mA
IIL
Low-Level Input Current
VCC= max. VIN = 0.5V
-2
mA
IOS
Short Circuit Output Current VCC= max. VOUT = 0.
-40
-100
mA
ICCH High-Level Supply Current
VCC= max. VIN = OPEN
75
mA
ICCL
Low-Level Supply Current
VCC= max. VIN = 0
75
mA
TRO
Output Rise Time
Td
≤ 500 nS (0.75 to 2.4 Volts)
4
nS
NH
Fanout High-Level Output
VCC= max. VOH = 2.7V
20 TTL LOAD
NL
Fanout Low-Level Output
VCC= max. VOL = 0.5V
10 TTL LOAD
DC Electrical Characteristics
Parameter
Test Conditions
Min
Max Unit
VCC
Supply Voltage
4.75
5.25
V
VIH
High-Level Input Voltage
2.0
V
VIL
Low-Level Input Voltage
0.8
V
IIK
Input Clamp Current
-18
mA
IOH
High-Level Output Current
-1.0
mA
IOL
Low-Level Output Current
20
mA
PW*
Pulse Width of Total Delay
40
%
d*
Duty Cycle
40
%
TA
Operating Free-Air Temperature
0
+70
°C
Recommended
Operating Conditions
Min
Max
Unit
*These two values are inter-dependent.
Schematic
DSD9430 Rev. A 2/5/96
QAF-CSO1 Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
Fractional = ± 1/32
.XX = ± .030
.XXX = ± .010
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791
E L E C T R O N I C S
I N C .
8
1
7
OUTPUT
GROUND
INPUT
14
VCC
.365
Max.
.780 Max.
.280
Max.
PCA
EP9430-5
Date Code
.010
Typ.
.150 Typ.
.020
.040
.250
Max.
.020
Typ.
White Dot
Pin#1
.600
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP9430-275 | Tapped Delay Line |
| EP9430-30 | Single Digitally Controlled (XDCP™) Potentiometer; Temperature Range: 0°C to 70°C; Package: 14-TSSOP |
| EP9430-300 | Tapped Delay Line |
| EP9430-55 | Dual Digitally Controlled Potentiometer (XDCP™); Temperature Range: 0°C to 70°C; Package: 20-PDIP |
| EP9430-6 | Tapped Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP9430-275 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:14 Pin DIP Single Output TTL Compatible Active Delay Lines |
| EP9430-30 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:14 Pin DIP Single Output TTL Compatible Active Delay Lines |
| EP9430-300 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:14 Pin DIP Single Output TTL Compatible Active Delay Lines |
| EP9430-35 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:14 Pin DIP Single Output TTL Compatible Active Delay Lines |
| EP9430-350 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:14 Pin DIP Single Output TTL Compatible Active Delay Lines |
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