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參數資料
| 型號： | EP9749-225 |
| 中文描述： | 抽頭延遲線 |
| 文件頁數： | 1/1頁 |
| 文件大小： | 11K |
| 代理商： | EP9749-225 |
Mini SIL Single Output TTL Compatible Active Delay Lines
TIME DELAYS * (nS)
PART
TIME DELAYS * (nS)
PART
±5% or ±2 nS
NUMBER
±5% or ±2 nS
NUMBER
5
EP9748-5
60
EP9748-60
10
EP9748-10
75
EP9748-75
15
EP9748-15
100
EP9748-100
20
EP9748-20
125
EP9748-125
25
EP9748-25
150
EP9748-150
30
EP9748-30
175
EP9748-175
35
EP9748-35
200
EP9748-200
40
EP9748-40
225
EP9748-225
45
EP9748-45
250
EP9748-250
50
EP9748-50
Whichever is greater.
*Delay Times referenced from input to leading edges at 25°C, 5.0V, with no load.
Package Dimensions
VOH
High-Level Output Voltage
VCC= min. VIL= max. I OH = max 2.7
V
VOL
Low-Level Output Voltage
VCC= min. VIH = min. I OL= max
0.5
V
VIK
Input Clamp Voltage
VCC= min. II = IIK
-1.2
V
IIH
High-Level Input Current
VCC= max. VIN = 2.7V
50
A
VCC= max. VIN = 5.25V
1.0
mA
IIL
Low-Level Input Current
VCC= max. VIN = 0.5V
-2
mA
IOS
Short Circuit Output Current
VCC= max. VOUT = 0.
-40
-100
mA
ICCH High-Level Supply Current
VCC= max. VIN = OPEN
75
mA
ICCL Low-Level Supply Current
VCC= max. VIN = 0
75
mA
TRO
Output Rise Time
Td
≤ 500 nS (0.75 to 2.4 Volts)
4
nS
NH
Fanout High-Level Output
VCC= max. VOH = 2.7V
20 TTL LOAD
NL
Fanout Low-Level Output
VCC= max. VOL = 0.5V
10 TTL LOAD
DC Electrical Characteristics
Parameter
Test Conditions
Min
Max Unit
VCC
Supply Voltage
4.75
5.25
V
VIH
High-Level Input Voltage
2.0
V
VIL
Low-Level Input Voltage
0.8
V
IIK
Input Clamp Current
-18
mA
IOH
High-Level Output Current
-1.0
mA
IOL
Low-Level Output Current
20
mA
PW*
Pulse Width of Total Delay
40
%
d*
Duty Cycle
40
%
TA
Operating Free-Air Temperature
0
+70
°C
Recommended
Operating Conditions
Min
Max
Unit
*These two values are inter-dependent.
Schematic
EIN
Pulse Input Voltage
3.2
Volts
PW
Pulse Width % of Total Delay
110
%
TRI
Pulse Rise Time (0.75 - 2.4 Volts)
2.0
nS
PRR
Pulse Repetition Rate @ Td
≤ 200 nS
1.0
MHz
Pulse Repetition Rate @ Td > 200 nS
100
KHz
VCC
Supply Voltage
5.0
Input Pulse Test Conditions @ 25° C
Unit
Volts
DSD9748 Rev. A 2/5/96
QAF-CSO1 Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
Fractional = ± 1/32
.XX = ± .030
.XXX = ± .010
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791
E L E C T R O N I C S
I N C .
4
2
5
OUTPUT
GROUND
INPUT
1
VCC
.010 x .018
.480 Max.
.200
.150 Typ.
.015
Min.
.300 Max.
.190
Max
PCA
EP9748-5
D.C.
C
L
.100
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相關代理商/技術參數 |
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|---|---|
| EP9749-250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| EP9749-300 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| EP9749-350 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| EP9749-400 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| EP9749-420 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
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