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參數(shù)資料
型號: EPF10K100EQI208-2
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 1/120頁
文件大小: 1901K
代理商: EPF10K100EQI208-2
Altera Corporation
1
FLEX 10KE
Embedded Programmable
Logic Family
September 2000, ver. 2.10
Data Sheet
A-DS-F10KE-02.10
Features...
s
Embedded programmable logic devices (PLDs), providing
system-on-a-programmable-chip integration in a single device
Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
Logic array for general logic functions
s
High density
30,000 to 200,000 typical gates (see Tables 1 and 2)
Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be
used without reducing logic capacity
s
System-level features
MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
Low power consumption
Bidirectional I/O performance (tSU and tCO) up to 212 MHz
Fully compliant with the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2
for 3.3-V operation at
33 MHz or 66 MHz
-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2
, for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
f For information on 5.0-V FLEX 10K or 3.3-V FLEX 10KA devices, see the
Table 1. FLEX 10KE Device Features
Feature
EPF10K30E
EPF10K50E
EPF10K50S
EPF10K100B
Typical gates (1)
30,000
50,000
100,000
Maximum system gates
119,000
199,000
158,000
Logic elements (LEs)
1,728
2,880
4,992
EABs
6
10
12
Total RAM bits
24,576
40,960
24,576
Maximum user I/O pins
220
254
191
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