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參數資料
| 型號： | EPM240GT100C5N |
| 廠商： | Altera |
| 文件頁數： | 1/6頁 |
| 文件大小： | 0K |
| 描述： | IC MAX II CPLD 240 LE 100-TQFP |
| 產品變化通告： | Bond Wire Change 4/Sept/2008 |
| 標準包裝： | 270 |
| 系列： | MAX® II |
| 可編程類型： | 系統內可編程 |
| 最大延遲時間 tpd(1)： | 4.7ns |
| 電壓電源 - 內部： | 1.71 V ~ 1.89 V |
| 邏輯元件/邏輯塊數目： | 240 |
| 宏單元數： | 192 |
| 輸入/輸出數： | 80 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 603 (CN2011-ZH PDF) |
| 其它名稱： | 544-1397 EPM240GT100C5N-ND |
1. Introduction
Introduction
The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m,
6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128
to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices
offer high I/O counts, fast performance, and reliable fitting versus other CPLD
architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed to reduce
cost and power while providing programmable solutions for applications such as bus
bridging, I/O expansion, power-on reset (POR) and sequencing control, and device
configuration control.
Features
The MAX II CPLD has the following features:
■
Low-cost, low-power CPLD
■
Instant-on, non-volatile architecture
■
Standby current as low as 25 A
■
Provides fast propagation delay and clock-to-output times
■
Provides four global clocks with two clocks available per logic array block (LAB)
■
UFM block up to 8 Kbits for non-volatile storage
■
MultiVolt core enabling external supply voltages to the device of either
3.3 V/2.5 V or 1.8 V
■
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
■
Bus-friendly architecture including programmable slew rate, drive strength,
bus-hold, and programmable pull-up resistors
■
Schmitt triggers enabling noise tolerant inputs (programmable per pin)
■
I/Os are fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 66 MHz
■
Supports hot-socketing
■
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry
compliant with IEEE Std. 1149.1-1990
■
ISP circuitry compliant with IEEE Std. 1532
MII51001-1.9
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EPM240GT100C5RR | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 1.8V 100-Pin TQFP |
| EPM240GT100I | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM240GT100I5 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX II 192 Macro 80 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM240GT100I5N | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX II 192 Macro 80 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM240GT100I5NRR | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 1.8V 100-Pin TQFP |
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