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參數(shù)資料
| 型號： | EPM7128ALC84-7 |
| 文件頁數(shù)： | 1/60頁 |
| 文件大小： | 1030K |
| 代理商： | EPM7128ALC84-7 |
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Includes
MAX 7000AE
Altera Corporation
1
MAX 7000A
Programmable Logic
Device
April 2001, ver. 4.0
Data Sheet
A-DS-M7000A-04.0
Features...
I
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX) architecture (see Table 1)
I
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
–
MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
–
EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
I
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
I
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
I
Enhanced ISP features
–
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
–
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
–
Pull-up resistor on I/O pins during in-system programming
I
Pin-compatible with the popular 5.0-V MAX 7000S devices
I
High-density PLDs ranging from 600 to 10,000 usable gates
I
4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
f For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family
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