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參數資料
型號: EPM7256AETI144-7N
廠商: Altera
文件頁數: 1/64頁
文件大小: 0K
描述: IC MAX 7000 CPLD 256 144-TQFP
產品變化通告: Bond Wire Change 4/Sept/2008
標準包裝: 180
系列: MAX® 7000A
可編程類型: 系統內可編程
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數目: 16
宏單元數: 256
門數: 5000
輸入/輸出數: 120
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
包裝: 托盤
其它名稱: 544-2063
EPM7256AETI144-7N-ND
Includes
MAX 7000AE
Altera Corporation
1
MAX 7000A
Programmable Logic
Device
September 2003, ver. 4.5
Data Sheet
DS-M7000A-4.5
Features...
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX) architecture (see Table 1)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
Extended temperature range
f For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
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EPM7256AETI144-7 IC MAX 7000 CPLD 256 144-TQFP
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