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參數(shù)資料
| 型號： | EV-ADF4157SD1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4157 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4157 |
| 主要屬性： | 單路分數(shù)-N PLL |
| 次要屬性： | 6GHz |
| 已供物品： | 板 |
High Resolution 6 GHz Fractional-N
Frequency Synthesizer
Data Sheet
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2007–2012 Analog Devices, Inc. All rights reserved.
FEATURES
RF bandwidth to 6 GHz
25-bit fixed modulus allows subhertz frequency resolution
2.7 V to 3.3 V power supply
Separate V
P allows extended tuning voltage
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the following frequency synthesizers:
ADF4110/ADF4111/ADF4112/ADF4113/
ADF4106/ADF4153/ADF4154/ADF4156
Cycle slip reduction for faster lock times
APPLICATIONS
Satellite communications terminals, radar equipment
Instrumentation equipment
Personal mobile radio (PMR)
Base stations for mobile radio
Wireless handsets
GENERAL DESCRIPTION
The ADF4157 is a 6 GHz fractional-N frequency synthesizer with
a 25-bit fixed modulus, allowing subhertz frequency resolution
at 6 GHz. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. There is a Σ-Δ based fractional interpolator to allow
programmable fractional-N division. The INT and FRAC values
define an overall N divider, N = INT + (FRAC/225). The ADF4157
features cycle slip reduction circuitry, which leads to faster lock
times without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
LOCK
DETECT
N COUNTER
CP
RFCP3 RFCP2
RFCP4
RFCP1
REFERENCE
DATA
LE
32-BIT
DATA
REGISTER
CLK
REFIN
AVDD
AGND
VDD
DGND
RDIV
SDOUT
NDIV
DGND
CPGND
DVDD
VP
CE
RSET
RFINA
RFINB
OUTPUT
MUX
MUXOUT
–
+
HIGH Z
PHASE
FREQUENCY
DETECTOR
ADF4157
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
225
FRACTION
REG
INTEGER
REG
CURRENT
SETTING
×2
DOUBLER
5-BIT
R COUNTER
CHARGE
PUMP
CSR
÷2
DIVIDER
05874-
001
Figure 1.
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