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參數資料
| 型號： | EVAL-AD5373EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/29頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5373 |
| 產品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數量： | 32 |
| 位數： | 14 |
| 采樣率（每秒）： | 540k |
| 數據接口： | 串行 |
| 設置時間： | 20µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5373 |
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32-Channel, 16-/14-Bit,
Serial Input, Voltage Output DAC
AD5372/AD5373
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2007–2011 Analog Devices, Inc. All rights reserved.
FEATURES
32-channel DAC in a 64-lead LQFP and 64-lead LFCSP
AD5372/AD53731 guaranteed monotonic to 16/14 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of 4 V to +8 V
Multiple, independent output voltage spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
SERIAL
INTERFACE
05
81
5
-00
1
SDI
DVCC
VDD
VSS AGND DGND
SCLK
SDO
SYNC
BUSY
RESET
CLR
STATE
MACHINE
CONTROL
REGISTER
AD5372/
AD5373
X1 REGISTER
n = 16 FOR AD5372
n = 14 FOR AD5373
M REGISTER
C REGISTER
DAC 0
REGISTER
OFS0
REGISTER
GROUP 2 TO GROUP 3
ARE IDENTICAL TO GROUP 1
VREF1 SUPPLIES
GROUP 1 TO GROUP 3
X2A REGISTER
X2B REGISTER
BUFFER
GROUP 0
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
VOUT7
SIGGND0
SIGGND1
SIGGND3
SIGGND2
VOUT16
TO
VOUT31
LDAC
n
14
n
A/
B
MU
X
MU
X
2
OFFSET
DAC 0
X1 REGISTER
M REGISTER
C REGISTER
DAC 7
REGISTER
X2A REGISTER
X2B REGISTER
n
A/
B
MU
X
MU
X
2
DAC 7
X1 REGISTER
A/B SELECT
REGISTER
M REGISTER
C REGISTER
TO
MUX 2s
DAC 0
REGISTER
OFS1
REGISTER
X2A REGISTER
X2B REGISTER
BUFFER
GROUP 1
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
n
8
n
14
n
A/
B
MU
X
MU
X
2
OFFSET
DAC 1
DAC 0
X1 REGISTER
M REGISTER
C REGISTER
DAC 7
REGISTER
X2A REGISTER
X2B REGISTER
n
A/
B
MU
X
MU
X
2
DAC 7
VREF1
A/B SELECT
REGISTER
TO
MUX 2s
8
Figure 1.
1 Protected by U.S. Patent No. 5,969,657.
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