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參數資料
| 型號： | EVAL-AD7195EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/45頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7195 |
| 設計資源： | EVAL-AD7195EBZ Schematic AD7195 Gerber Files |
| 標準包裝： | 1 |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | AD7195 |
| 次要屬性： | 圖形用戶界面，USB 接口 |
| 已供物品： | 板 |
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4.8 kHz, Ultralow Noise, 24-Bit
Sigma-Delta ADC with PGA and AC Excitation
AD7195
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2010 Analog Devices, Inc. All rights reserved.
FEATURES
AC or DC sensor excitation
RMS noise: 8.5 nV at 4.7 Hz (gain = 128)
16 noise-free bits at 2.4 kHz (gain = 128)
Up to 22.5 noise-free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
2 differential/4 pseudo differential input channels
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
Power supply
AVDD: 4.75 V to 5.25 V
DVDD: 2.7 V to 5.25 V
Current: 6 mA
Temperature range: –40°C to +105°C
Package: 32-lead LFCSP
INTERFACE
3-wire serial
SPI, QSPI, MICROWIRE, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Strain gage transducers
Pressure measurement
Temperature measurement
Chromatography
PLC/DCS analog input modules
Data acquisition
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7195 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can be interfaced directly to the ADC. The AD7195
contains ac excitation, which is used to remove dc-induced
offsets from bridge sensors.
The device can be configured to have two differential inputs or
four pseudo differential inputs. The on-chip channel sequencer
allows several channels to be enabled, and the AD7195 sequentially
converts on each enabled channel. This simplifies communication
with the part. The on-chip 4.92 MHz clock can be used as the
clock source to the ADC or, alternatively, an external clock or
crystal can be used. The output data rate from the part can be
varied from 4.7 Hz to 4.8 kHz.
The device has two digital filter options. The choice of filter
affects the rms noise/noise-free resolution at the programmed
output data rate, the settling time, and the 50 Hz/60 Hz rejec-
tion. For applications that require all conversions to be settled,
the AD7195 includes a zero latency feature.
The part operates with a 5 V analog power supply and a digital
power supply from 2.7 V to 5.25 V. It consumes a current of
6 mA. It is housed in a 32-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
MCLK1 MCLK2
DVDD DGND
REFIN(+)
REFIN(–)
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
AD7195
REFERENCE
DETECT
SERIAL
INTERFACE
AND
CONTROL
LOGIC
TEMP
SENSOR
AC
EXCITATION
CLOCK
CIRCUITRY
DOUT/RDY
DIN
SCLK
CS
SYNC
AVDD
AGND
Σ-Δ
ADC
PGA
MUX
ACX1
ACX2
08
77
1-
00
1
Figure 1.
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