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參數資料
| 型號： | EVAL-AD7841EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/13頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7841 |
| 產品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數量： | 8 |
| 位數： | 14 |
| 采樣率（每秒）： | 32k |
| 數據接口： | 并聯 |
| 設置時間： | 31µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD7841 |
| 相關產品： | AD7841BSZ-REEL-ND - IC DAC 14BIT OCTAL VOUT 44-MQFP AD7841ASZ-REEL-ND - IC DAC 14BIT OCTAL VOUT 44-MQFP AD7841BSZ-ND - IC DAC 14BIT OCTAL V-OUT 44-MQFP AD7841ASZ-ND - IC DAC 14BIT OCTAL V-OUT 44MQFP |
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7841
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Octal 14-Bit, Parallel Input,
Voltage-Output DAC
FUNCTIONAL BLOCK DIAGRAM
DAC
REG
A
INPUT
REG
A
DAC E
AD7841
DB13
DB0
WR
CS
A0
A1
A2
LDAC
RR
R
DAC
REG
B
INPUT
REG
B
DAC
REG
C
INPUT
REG
C
DAC
REG
D
INPUT
REG
D
DAC
REG
E
INPUT
REG
E
DAC
REG
F
INPUT
REG
F
DAC
REG
G
INPUT
REG
G
DAC
REG
H
INPUT
REG
H
14
DAC D
DAC C
DAC F
DAC B
DAC A
DAC G
DAC H
VCC
VSS
VDD
VREF(+)
AB
VREF(–)
AB
DUTGND
CD
DUTGND
AB
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
DUTGND
GH
DUTGND
EF
VREF(–)
CDEF
VREF(+)
CDEF
VREF(–)
GH
VREF(+)
GH
GND
CLR
ADDRESS
DECODE
14
FEATURES
Eight 14-Bit DACs in One Package
Voltage Outputs
Offset Adjust for Each DAC Pair
Reference Range of
5 V
Maximum Output Voltage Range of
10 V
15 V
10% Operation
Clear Function to User-Defined Voltage
44-Lead MQFP Package
APPLICATIONS
Automatic Test Equipment
Process Control
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7841 contains eight 14-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of
±10 V
from reference voltages of
±5 V.
The AD7841 accepts 14-bit parallel loaded data from the exter-
nal bus into one of the input registers under the control of the
WR, CS, and DAC channel address pins, A0–A2.
The DAC outputs are updated on reception of new data into
the DAC registers. All the outputs may be updated simulta-
neously by taking the
LDAC input low.
Each DAC output is buffered with a gain-of-two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
The AD7841 is available in a 44-lead MQFP package.
REV. B
Fax: 781/461-3113
1999-2011 Analog Devices, Inc. All rights reserved.
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