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| 型號： | EVAL-ADCMP601BKSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADCMP601 SC70-5 |
| 標準包裝： | 1 |
| 主要目的： | 比較器，單路 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADCMP601 |
| 主要屬性： | CMOS 和 TTL 兼容輸出 |
| 次要屬性： | 鎖銷啟用引腳 |
| 已供物品： | 板 |
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparators
ADCMP600/ADCMP601/ADCMP602
FEATURES
Fully specified rail to rail at V
CC = 2.5 V to 5.5 V
Input common-mode voltage from 0.2 V to V
CC + 0.2 V
Low glitch CMOS-/TTL-compatible output stage
3.5 ns propagation delay
10 mW at 3.3 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 50 dB
Improved replacement for MAX999
40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current/voltage-controlled oscillators
Automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
LE/HYS
(EXCEPT ADCMP600)
Q OUTPUT
SDN
(ADCMP602 ONLY)
ADCMP600/
ADCMP601/
ADCMP602
05914-
001
Figure 1.
GENERAL DESCRIPTION
The ADCMP600, ADCMP601, and ADCMP602 are very fast
comparators fabricated on XFCB2, an Analog Devices, Inc.
proprietary process. These comparators are exceptionally
versatile and easy to use. Features include an input range from
GND 0.5 V to VCC + 0.2 V, low noise, TTL-/CMOS-compatible
output drivers, and latch inputs with adjustable hysteresis
and/or shutdown inputs.
The device offers 5 ns propagation delay with 10 mV overdrive
on 3 mA typical supply current.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a 0.5 V to +2.8 V
input signal range up to a +5.5 V positive supply with a 0.5 V
to +5.8 V input signal range. Split input/output supplies with no
sequencing restrictions on the ADCMP602 support a wide
input signal range while still allowing independent output
swing control and power savings.
The TTL-/CMOS-compatible output stage is designed to drive
up to 5 pF with full timing specs and to degrade in a graceful
and linear fashion as additional capacitance is added. The
comparator input stage offers robust protection against large
input overdrive, and the outputs do not phase reverse when the
valid input signal range is exceeded. Latch and programmable
hysteresis features are also provided with a unique single-pin
control option.
The ADCMP600 is available in 5-lead SC70 and SOT-23
packages, the ADCMP601 is available in a 6-lead SC70 package,
and the ADCMP602 is available in an 8-lead MSOP package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2006–2011 Analog Devices, Inc. All rights reserved.
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