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| 型號： | EVAL-ADCMP605BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADCMP605 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 比較器，單路 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADCMP605 |
| 主要屬性： | LVDS 兼容輸出 |
| 已供物品： | 板 |
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply LVDS Comparators
ADCMP604/ADCMP605
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006–2007 Analog Devices, Inc. All rights reserved.
FEATURES
Fully specified rail to rail at VCCI = 2.5 V to 5.5 V
Input common-mode voltage from 0.2 V to VCCI + 0.2 V
Low glitch LVDS-compatible output stage
1.6 ns propagation delay
37 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB
40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
VP NONINVERTING
INPUT
VN INVERTING
INPUT
SDN INPUT
Q OUTPUT
VCCO
(ADCMP605 ONLY)
VCCI
Q OUTPUT
LE/HYS INPUT
(ADCMP605
ONLY)
ADCMP604/
ADCMP605
LVDS
0
591
6-
00
1
Figure 1.
GENERAL DESCRIPTION
The ADCMP604/ADCMP605 are very fast comparators
fabricated on the Analog Devices, Inc. proprietary XFCB2
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from VEE 0.5 V to VCCI +
0.2 V, low noise, LVDS-compatible output drivers, and
TTL/CMOS latch inputs with adjustable hysteresis and/or shut-
down inputs.
The devices offer 1.5 ns propagation delays with 1 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single 2.5 V positive supply and a 0.5 V to +2.7 V input
signal range up to a 5.5 V positive supply with a 0.5 V to +5.7 V
input signal range. Split input/output supplies, with no sequencing
restrictions on the ADCMP605, support a wide input signal
range with greatly reduced power consumption.
The LVDS-compatible output stage is designed to drive any
standard LVDS input. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. High
speed latch and programmable hysteresis features are also provided
in a unique single-pin control option.
The ADCMP604 is available in a 6-lead SC70 package, and the
ADCMP605 is available in a 12-lead LFCSP.
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參數(shù)描述 |
|---|---|
| EVAL-ADCMP605BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
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