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參數資料
| 型號： | EVAL-ADF5002EB2Z |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/12頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADF5002 |
| 設計資源： | ADF500x Gerber Files |
| 標準包裝： | 1 |
| 類型： | 預定標器 |
| 頻率： | 4GHz ~ 18GHz |
| 適用于相關產品： | ADF5002 |
| 已供物品： | 板 |
4 GHz to 18 GHz
Divide-by-8 Prescaler
ADF5002
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2010 Analog Devices, Inc. All rights reserved.
FEATURES
Divide-by-8 prescaler
High frequency operation: 4 GHz to 18 GHz
Integrated RF decoupling capacitors
Low power consumption
Active mode: 30 mA
Power-down mode: 7 mA
Low phase noise: 153 dBc/Hz
Single dc supply: 3.3 V compatible with ADF4xxx PLLs
Temperature range: 40°C to +105°C
Small package: 3 mm × 3 mm LFCSP
APPLICATIONS
PLL frequency range extender
Point-to-point radios
VSAT radios
Communications test equipment
GENERAL DESCRIPTION
The ADF5002 prescaler is a low noise, low power, fixed RF
divider block that can be used to divide down frequencies as
high as 18 GHz to a lower frequency suitable for input to a
provides a divide-by-8 function. The ADF5002 operates from
a 3.3 V supply and has differential 100 Ω RF outputs to allow
direct interface to the differential RF inputs of PLLs such as
FUNCTIONAL BLOCK DIAGRAM
DIVIDE
BY 8
BIAS
ADF5002
CE
GND
RFIN
VDDx
RFOUT
100
50
100
1pF
3pF
1pF
08
75
3-
0
01
Figure 1.
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