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參數(shù)資料
| 型號(hào)： | F49L800UA-70T |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| 中文描述： | 512K X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP1-48 |
| 文件頁數(shù)： | 17/47頁 |
| 文件大小： | 435K |
| 代理商： | F49L800UA-70T |
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ES MT
7.4 More Device Operations
Hardware Data Protection
F49L800UA/F49L800BA
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision: 1.2 17/47
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware
data protection measures prevent accidental erasure or
programming, which might otherwise be caused by
spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than VLKO, the device does not accept
any write cycles. This protects data during V
CC
power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device
resets. Subsequent writes are ignored until V
CC
is
greater than V
LKO
. The system must provide the proper
signals to the control pins to prevent unintentional writes
when V
CC
is greater than V
LKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on
CE
or
WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of
OE
=
V
IL
,
CE
= V
IH
or
WE
= V
IH
. To initiate a write cycle,
CE
and
WE
must be a logical zero while
OE
is a
logical one.
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between
its V
CC
and GND.
Power-Up Sequence
The device powers up in the Read Mode. In addition, the
memory contents may only be altered after successful
completion of the predefined command sequences.
Power-Up Write Inhibit
If
WE
=
CE
= V
IL
and
OE
= V
IH
during power up, the
device does not accept commands on the rising edge of
WE
. The internal state machine is automatically reset to
reading array data on power-up.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| F49L800UA-70TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| F49L800UA-70TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| F49L800UA-90T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| F49L800UA-90TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| F49L800UA-90TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
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