
FAN1655
PRODUCT SPECIFICATION
REV. 1.1.4 3/24/04
5
Applications Information
Output Capacitor selection
The JEDEC specification for DDR termination requires that
VTT stay within ±40mV of VREF, which must track
VDDQ/2 within 1%. During the initial load transient, the
output capacitor keeps the output within spec. To stay within
the 40mV window, the “load step” due to the load transient
current dropping across the output capacitor’s ESR should be
kept to around 25mV: where ESR <
I is the maximum load current.
is given in m
, and
For example, to handle a 3A maximum load transient, the
ESR should be no greater than 8m
capacitor must be able to hold the load in spec while the
regulator recovers (about 15μS). A minimum value of 470μF
is recommended.
. Furthermore, the output
These requirements can be achieved by a combination of
capacitors. FAN1655 requires a minimum of 5m
in the output and is not stable with all-ceramic output
capacitors.
of ESR
Power Dissipation and Derating
The maximum output current (sink or source) for a 1.25V
output is:
where P
D(MAX)
is the maximum power dissipation which is:
where T
and T
J(MAX)
is the operating ambient temperature.
is the maximum die temperature of the IC
A
FAN1655 has an internal thermal limit at 150°C, which
defines T
J(MAX)
. For the SOIC-14 package,
88°C/W. Using equation 2, the maximum dissipation at
T
A
= 25°C is 1.4W, which is its rated maximum dissipation.
θ
JA
is given at
The e-TSSOP or MLP package, however, use the PCB
copper to cool the IC through the thermal pad on the package
bottom. For maximum dissipation, this pad should be
soldered to the PCB copper, with as much copper area as
possible surrounding it to cool the package. Thermal vias
should be placed as close to the thermal pad as possible to
transfer heat to other layers of copper on the PCB. With large
areas of PCB copper for heat sinking, a
can easily be achieved.
θ
JA
of under 40°C/W
I
25
I
OUT MAX
)
P
)
------1.25
=
(1)
P
D MAX
)
T
----------------------------------
T
A
–
JA
=
(2)