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參數資料
| 型號： | FAN4800 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Low Start-Up Current PFC/PWM Controller Combos |
| 中文描述： | 低啟動電流式PFC / PWM控制器功放音箱 |
| 文件頁數： | 11/19頁 |
| 文件大小： | 369K |
| 代理商： | FAN4800 |
FAN4800
11
RAMP1
V
RMS
OS C ILLATOR
4
3
15
PFC I
LIMIT
2
POWER FAC TOR C ORREC TOR
G AIN
MODULATOR
V
F B
I
S E NS E
7.5V
RE FERENC E
7
S
R
Q
S
R
Q
I
AC
IE AO
VE AO
V
c c
V
RE F
PFC OUT
3.5k
3.5k
2.5V
0.5V
2.78V
- 1V
12
14
0.3V
Low Power
Detec tor
Vcc
17.9V
TRI- F AULT
Vcc OVP
PF C OVP
PFC C MP
C LK
13
16
1
Figure 1. PFC Section Block Diagram
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a neg-
ative resistor because an increase in the input voltage
to the PWM causes a decrease in the input current. This
response dictates the proper compensation of the two
transconductance error amplifiers.
Figure 2 shows the types of compensation networks
most commonly used for the voltage and current error
amplifiers, along with their respective return points. The
current loop compensation is returned to V
REF
to pro-
duce a soft-start characteristic on the PFC: As the refer-
ence voltage increases from zero volts, it creates a
differentiated voltage on I
EAO
which prevents the PFC
from immediately demanding a full duty cycle on its
boost converter.
PFC Voltage Loop
There are two major concerns when compensating the
voltage loop error amplifier, V
EAO
: Stability and tran-
sient response. Optimizing interaction between tran-
sient response and stability requires that the error
amplifier’s open loop crossover frequency should be 1/
2 that of the line frequency, or 23Hz for 47Hz line (low-
est anticipated international power frequency). The gain
vs. input voltage of the FAN4800’s voltage error ampli-
fier, V
EAO
has a specially shaped non-linearity so that
under steady state operating conditions the transcon-
ductance of the error amplifier is at a local minimum.
Rapid perturbation in line or load conditions will cause
the input to the voltage error amplifier (VFB) to deviate
from its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier will in-
crease significantly, as shown in the Figure A of the
Typical Performance Characteristics.
This raises the
gain-bandwidth product of the voltage loop, resulting in
a much more rapid voltage loop response to such per-
turbations than would occur with conventional linear
gain characteristics.
The Voltage Loop Gain(S)
is given by
:
where
Zc : Compensation network for the voltage loop
GMv: Transconductance of VEAO
P
IN
: Average PFC input power
VZOUTDC: PFC boost output voltage; typical designed
value is 380V.
C
DC
: PFC boost output capacitor
PFC Current Loop
The compensation of the current amplifier, I
EAO,
is sim-
ilar to that of the voltage error amplifier, V
EAO
, with the
exception of the choice of crossover frequency. The
crossover frequency of the current amplifier should be
at least 10 times that of the voltage amplifier, to prevent
interaction with the voltage loop. It should also be limit-
ed to less than 1/6
th
of the switching frequency, e.g.
16.7kHz for a 100kHz switching frequency.
The Current Loop Gain(S) is given by:
where
Z
CI
: Compensation network for the current loop
GM
I
: Transconductance of IEAO
V
OUTDC
: PFC boost output voltage; typical designed
value is 380V. The equation uses the worst condition to
VEAO
---------------------
VOUT
2.5V
---------------------
×
VFB
---------------------
×
=
×
V2OUTDC
VEAO
×
S
×
CDC
×
----------------------------------------------------------------------------------------
GMV
×
ZC
×
≈
DOFF
S
-------------------------------
IEAO
2.5V
--------------------
×
VISENSE
-------------------------------
×
=
L
×
×
-----------------------------------------
GMI
×
ZCI
×
≈
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