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參數(shù)資料
| 型號： | FAN5018B |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 6-Bit VID Controller 2-4 Phase VR10.X Controller |
| 中文描述： | 6期西元控制器2-4位的VR10.X控制器 |
| 文件頁數(shù)： | 25/30頁 |
| 文件大小： | 509K |
| 代理商： | FAN5018B |
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PRODUCT SPECIFICATION
FAN501
8
B
REV. 1.0.0 Jul/15/05
25
Choosing the closest standard values for these components
yields: C
A
= 390pF, R
A
= 16.9k
Ω
, C
B
= 1.5nF, and C
FB
=
33pF.
C
IN
Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of
the high-side MOSFET is approximately a square wave with
a duty ratio equal to n (V
OUT
/V
IN
) and an amplitude of one-
nth of the maximum output current. To prevent large voltage
transients, use a low ESR input capacitor sized for the maxi-
mum rms current. The maximum rms capacitor current is
given by:
Figure 6. Typical Transient Response for Design Example
Note that the capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes it
advisable to further derate the capacitor, or to choose a
capacitor rated at a higher temperature than required. Several
capacitors may be placed in parallel to meet size or height
requirements in the design. In this example, the input
capacitor bank is formed by three 2200μF, 16V Nichicon
capacitors with a ripple current rating of 3.5A each.
To reduce the input-current di/dt to below the recommended
maximum of 0.1A/μs, insert an additional small inductor (L
> 1μH @ 15A) between the converter and the supply bus.
That inductor also acts as a filter between the converter and
the primary power source.
Tuning Procedure for the FAN501
8
B
DC Load Line Setting
1.
Build a circuit based on compensation values computed
from the design spreadsheet.
2.
Hook up DC load to circuit, turn on and verify opera-
tion. Also check for jitter at no-load and full-load.
3.
Measure output voltage at no-load (V
NL
). Verify it is
within tolerance.
Figure 7. Efficiency vs. Output Current
(Circuit of Figure 5)
4.
Measure output voltage at full-load cold (V
FLCOLD
).
Let board soak for ~10 minutes at full-load and measure
output (V
FLHOT
). If there is a change of more than a
couple of millivolts, adjust R
CS1
and R
CS2
using
Equations 35 and 37.
5.
Repeat Step 4 until cold and hot voltage measurements
remain the same.
6.
Measure output voltage from no-load to full-load using
5 Amp steps. Compute the loadline slope for each
change and then average to get overall loadline slope
(R
OMEAS
).
7.
If R
OMEAS
is off from R
O
by more than 0.05 m
Ω
,
use the following to adjust the R
PH
values:
8.
Repeat Steps 6 and 7 to check loadline and repeat
adjustments if necessary.
9.
Once the DC loadline adjustment is completed, do not
change R
PH
, R
CS1
, R
CS2
, or R
TH
for the rest of proce-
dure.
1
1
×
×
×
=
D
n
I
D
I
O
CRMS
(34)
A
A
I
CRMS
5
10
1
125
.
×
3
1
65
125
.
=
×
×
=
(
(
)
)
FLHOT
NL
FLCOLD
V
NL
OLD
CS
NEW
CS
V
V
V
R
R
×
=
)
(
)
(
(35)
80
100
60
40
20
0
20
0
40
OUTPUT CURRENT (A)
E
60
10
30
50
O
OMEAS
R
OLD
PH
NEW
PH
R
R
R
×
=
)
(
)
(
(36)
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