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參數資料
| 型號： | FAN5019B |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 6-Bit VID Controller 2-4 Phase VR10.X Controller |
| 中文描述： | 6期西元控制器2-4位的VR10.X控制器 |
| 文件頁數： | 26/30頁 |
| 文件大小： | 508K |
| 代理商： | FAN5019B |
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FAN5019B
PRODUCT SPECIFICATION
26
REV. 1.0.0 Jul/15/05
10. Measure the output ripple at no-load and full-load with a
scope and make sure it is within spec.
(37)
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1
1
C
TH
C
TH
OLD
CS
NEW
CS
OLD
CS
C
TH
OLD
CS
C
TH
OLD
CS
NEW
CS
o
o
o
o
R
R
R
R
R
R
R
R
R
R
×
+
×
+
=
AC Loadline Setting
11. Remove DC load from circuit and hook up dynamic
load.
12. Hook up scope to output voltage and set to DC coupling
with a time scale at 100μs/div.
13. Set dynamic load for a transient step of approximately
40A at 1kHz with 50% duty cycle.
14. Measure the output waveform (may have to use DC off-
set on scope to see waveform). Try to use a vertical
scale of 100 mV/div or finer.
15. You will see a waveform that looks something like
Figure 8. Use the horizontal cursors to measure V
ACDRP
and V
DCDRP
as shown.
NOTE:
DO NOT MEASURE THE UNDERSHOOT OR
OVERSHOOT THAT HAPPENS IMMEDIATELY AFTER
THE STEP.
100
Figure 8. AC Loadline Waveform
16. If the V
ACDRP
and V
DCDRP
are different by more than a
couple of millivolts, use Equation 38 to adjust C
CS
. You
may need to parallel different values to get the right one
since there are limited standard capacitor values avail-
able (it is a good idea to have locations for two capaci-
tors in the layout for this).
17. Repeat Steps 11 to 13 and repeat adjustments if
necessary. Once complete, do not change C
CS
for the
rest of the procedure.
18. Set the dynamic load step to the maximum step size (do
not use a step size larger than needed) and verify that the
output waveform is square (which means VACDRP and
VDCDRP are equal).
NOTE:
MAKE SURE LOAD
STEP SLEW RATE AND TURN-ON ARE SET FOR A
SLEW RATE OF ~150–250A/μs (for example, a load
step of 50A should take 200ns–300ns) WITH NO
OVERSHOOT. Some dynamic loads will have an
excessive turn-on overshoot if a minimum current is not
set properly (this is an issue if using a VTT tool).
Initial Transient Setting
19. With dynamic load still set at maximum step size,
expand the scope time scale to see 2μs/div to 5μs/div.
You will see a waveform that may have two overshoots
and one minor undershoot (see Figure 9). Here, V
DROOP
is the final desired value.
Figure 9. Transient Setting Waveform
20. If both overshoots are larger than desired, try making
the following adjustments in this order. (
NOTE
: If these
adjustments do not change the response, you are limited
by the output decoupling.) Check the output response
each time you make a change as well as the switching
nodes (to make sure it is still stable).
a. Make ramp resistor larger by 25% (R
RAMP
).
b. For V
TRAN1
, increase CB or increase switching fre-
quency.
c. For V
TRAN2
, increase R
A
and decrease C
A
by 25%.
21. For load release (see Figure 10), if V
TRANREL
is larger
than V
TRAN1
(see Figure 9), you do not have enough
output capacitance. You will either need more capaci-
tance or need to make the inductor values smaller (if
you change inductors, you need to start the design over
using the spreadsheet and this tuning procedure).
80
60
40
20
0
20
0
40
OUTPUT CURRENT (A)
E
60
10
30
50
DCDRP
V
ACDRP
OLD
CS
NEW
CS
V
C
C
×
=
)
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(38)
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