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參數資料
| 型號： | FAN5019MTCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩壓器 |
| 英文描述： | 6-Bit VID Controller 2-4 Phase VRM10.X Controller |
| 中文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數： | 5/30頁 |
| 文件大小： | 781K |
| 代理商： | FAN5019MTCX |
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PRODUCT SPECIFICATION
FAN5019
REV. 1.0.7 1/5/04
5
Electrical Specifications
(V
CC
= 12V, T
A
= 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Parameter
Error Amplifier
Output Voltage Range
Symbol
Conditions
Min.
Typ.
Max.
Units
V
COMP
0.5
-10
-12
3.5
+10
+12
V
Accuracy
V
FB
Relative to DAC Setting,
referenced to FBRTN,
CSSUM = CSCOMP,
Test Circuit 3
VCC=10V to 14V
VRM10
VRM9
mV
Line Regulation
V
FB
0.05
-15
150
500
20
77
%
μA
μA
μA
MHz
dB
Input Bias Current
I
FB
-13
-17
180
FBRTN Current
I
FBRTN
Output Current
I
O(ERR)
FB forced to V
OUT
– 3%
300
Gain Bandwidth Product
GBW
COMP = FB
DC Gain
C
COMP
= 10pF
VID Inputs
Input Low Voltage
V
IL(VID)
VRM10
VRM9
0.4
0.8
V
V
V
V
μA
μA
k
V
V
ns
ns
Input High Voltage
V
IH(VID)
VRM10
VRM9
0.8
2.0
-30
-2
35
1.0
2.2
400
400
Input Current, VID Low
I
IL(VID)
VID(X) = 0V
-20
Input Current, VID High
I
IH(VID)
VID(X) = 1.25V
2
Pull-up Resistance
R
VID
Internal
60
1.15
2.4
115
1.26
2.6
Internal Pull-up Voltage
VRM10
VRM9
VID Transition Delay Time
2
VID Code Change to FB Change
“No CPU” Detection
Turn-off Delay Time
2
VID Table Select
VID Code Change to 11111X to PWM
going low
To select VRM9 table
To select VRM10 table (becomes VID5)
Vtblsel
4
3.5
V
V
Oscillator
Frequency
f
OSC
200
155
4000
245
kHz
kHz
kHz
kHz
V
mV
Frequency Variation
f
PHASE
T
A
= +25°C, R
T
= 250k
, 4-Phase
T
A
= +25°C, R
T
= 115k
, 4-Phase
T
A
= +25°C, R
T
= 75k
, 4-Phase
200
400
600
2.0
Output Voltage
V
RT
R
T
= 100k
to GND
1.9
-50
2.1
+50
RAMPADJ Pin Accuracy
V
RAMPADJ
V
RAMPADJ
= Vdac = +2K (Vin–Vdac)/
(Rr+2k)
Current into RAMPADJ pin
RAMPADJ Input Current
I
RAMPADJ
0
100
μA
Current Sense Amplifier
Offset Voltage
V
OS(CSA)
CSSUM–CSREF, Test Circuit 1
-1.5
-50
+1.5
+50
mV
nA
MHz
Input Bias Current
I
BIAS(CSA)
Gain Bandwidth Product
GBW
COMP = FB
10
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
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