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參數(shù)資料
型號(hào): FAN5109MX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: MOSFETs
英文描述: Terminal Block; No. of Positions:9; Pitch Spacing:0.197"; Mounting Type:PC Board RoHS Compliant: Yes
中文描述: 3.5 A BUF OR INV BASED MOSFET DRIVER, PDSO8
封裝: 0.150 INCH, LEAD FREE, MS-012AA, SOIC-8
文件頁(yè)數(shù): 5/13頁(yè)
文件大小: 119K
代理商: FAN5109MX
5
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
Electrical Specifications
V
CC
= 12V, and T
apply over the full operating temperature range.
A
= 25°C using the circuit in Figure 4 unless otherwise noted. The denotes specifications which
Notes:
1.
2.
3.
4.
All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control.
Specifications guaranteed by design/characterization (not production tested).
For propagation delays, “tpdh” refers to low-to-high signal transition and “tpdl” refers to high-to-low signal transition.
Transition times are defined for 10% and 90% of DC values.
Parameter
Input Supply
Symbol
Conditions
Min.
Typ.
Max.
Unit
VCC Voltage Range
V
CC
6.4
12
13.5
V
VCC Current
OD Input
I
CC
OD = 0V
2.5
4
mA
Input High Voltage
V
IH (OD)
V
IL (OD)
2.5
V
Input Low Voltage
0.8
V
Input Hysteresis
550
mV
Input Current
I
OD
t
pdl(OD)
t
pdh(OD)
OD = 3.0V
–300
+300
nA
Propagation Delay
2
See Figure 5
25
40
ns
15
30
ns
PWM Input
Input High Voltage
V
IH(PWM)
V
IL(PWM)
I
IL(PWM)
3.5
V
Input Low Voltage
0.8
V
μ
Input Current
High-Side Driver
-1
+1
A
Output Resistance, Sourcing
R
HUP
V
BOOT
= -10V
– V
SW
= 12V
2.5
3.3
A
A
Source Current
2
V
DS
2.0
Output Resistance, Sinking
2
R
HDN
V
BOOT
= 10V
– V
SW
= 12V
1.1
1.5
Sink Current
V
DS
3.0
Transition Times
2,4
t
R(HDRV)
t
F(HDRV)
t
pdh(HDRV)
t
pdl(HDRV)
Figure 4
25
40
ns
15
25
ns
Propagation Delay
2,3
See Figure 6
40
55
ns
25
40
ns
Low-Side Driver
Output Resistance, Sourcing
R
LUP
2.0
2.6
A
A
Source Current
2
V
DS
= -10V
2.7
Output Resistance, Sinking
2
R
LDN
0.9
1.2
Sink Current
V
DS
= 10V
3.5
Transition Times
2,4
t
R(LDRV)
t
F(LDRV)
t
pdh(LDRV)
t
pdl(LDRV)
t
pdh(LDF)
Figure 4
20
30
ns
15
25
ns
Propagation Delay
2,3
See Figure 6
20
30
ns
15
25
ns
See Adaptive Gate
Drive Circuit
description (page 10)
160
ns
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