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參數(shù)資料
| 型號： | FAN5182 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller |
| 中文描述： | 可調(diào)輸出1，2或3相同步降壓控制器 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 788K |
| 代理商： | FAN5182 |
12
www.fairchildsemi.com
FAN5182 Rev. 1.0.1
F
Application Information
Design parameters for a typical high current point-of-load dc/dc
buck converter shown in Figure 5 are as follows:
Input voltage (V
IN
) = 12V
Output voltage (V
OUT
) = 1.8V
Duty cycle (D) = 0.15
Output current I
O
= 55A
Maximum output current (I
LIM
) = 110A
Number of phases (n) = 3
Switching frequency per phase (
f
SW
) = 250kHz
Setting the Clock Frequency
The FAN5182 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R
T
). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and the input and output capaci-
tors. With n = 3 for three phases, a clock frequency of 750kHz
sets the switching frequency (
f
SW
) of each phase to 250kHz,
which represents a practical trade-off between the switching
losses and the sizes of the output filter components.
Equation 1 shows that to achieve a 750kHz oscillator frequency,
the correct value for R
T
is
255k
.
Alternatively, the value for R
T
can be calculated using
(1)
where 4.7pF and 27k
are internal IC component values. For
good initial accuracy and frequency stability, a 1% resistor is
recommended. The closest standard 1% value for this design is
255k
.
Soft-Start and Current Limit Latch-off Delay Time
Because the soft start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set C
DLY
for the soft-start ramp. This
ramp is generated with a 20μA internal current source. The
value of R
DLY
has a second-order impact on the soft-start time
because it sinks part of the current source to ground. However,
as long as R
DLY
is kept greater than 200k
, this effect is minor.
The value for C
DLY
can be approximated using:
(2)
where
t
SS
is the desired soft-start time. Assuming an R
DLY
of
390k
and a desired soft-start time of 3ms, C
DLY
is 71nF. The
closest standard value for C
DLY
is 68nF. Once C
DLY
is chosen,
R
DLY
can be calculated for the current limit latch-off time using:
(3)
If the result for R
DLY
is less than 200k
, a smaller soft-start time
should be considered by recalculating the equation for C
DLY
, or
a longer latch-off time should be used. R
DLY
should never be
less than 200k
. In this example, a delay time of 9ms results in
R
DLY
= 259k
. The closest standard 1% value is 261k
.
Inductor Selection
The inductance determines the ripple current in the inductor.
Small inductance leads to high ripple current, which increases
the output ripple voltage and conduction losses in the MOS-
FETs, and vise versa. In any multiphase converters, it's recom-
mended to design the peak-peak inductor ripple current to be
less than 50% of the maximum inductor dc current.
Equation 4 shows the relationship among the inductance, oscil-
lator frequency, and peak-peak ripple current.
(4)
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
(5)
where R
X
is the ESR of output bulk capacitors.
Solving Equation 5 for a 20mV peak-to-peak output ripple volt-
age and 3m
R
X
yields
1
3
0.15
×
(
–
(
×
250kHz
20mV
×
If the resulting ripple voltage is too low, the inductance can be
reduced until the desired ripple voltage is achieved. In this
example, a 600nH inductor is a good starting point that pro-
duces a calculated ripple current of 6.6A. The inductor should
not saturate at the peak current of 21.6A, and should be able to
handle the total power dissipation created by the copper and
core loss.
Another important factor in the inductor design is the DCR,
which is used for measuring the phase current. A large DCR
can cause excessive power losses, whereas too small DCR can
increases measurement error. For this design, a DCR of 1.4m
was chosen.
Designing an Inductor
Once the inductance and DCR are known, the next step is to
either design an inductor or find a suitable standard inductor if
one exists. Inductor design starts with choosing appropriate
core material. Some candidate materials that have low core loss
at high frequencies are powder cores (e.g. Kool-Mμ from Mag-
netics, Inc., or from Micrometals) and gapped soft ferrite cores
(e.g. 3F3 or 3F4 from Philips). Powdered iron cores have higher
core loss, and are used for low cost applications.
The best choice for a core geometry is a closed-loop type, such
as a potentiometer core, a PQ/U/E core, or a toroid core.
Some useful references for magnetics design are
Magnetic Designer Software
Intusoft (www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-DC
Converters, by William T. McLyman, Kg Magnetics, Inc.,
ISBN 1883107008
R
T
×
n
f
SW
4.7pF
------------------1
27k
–
=
R
T
3
250kHz
4.7pF
×
----------------------1
27k
–
256k
=
=
C
DLY
20
μ
A
V
R
DLY
2
---------------------
–
t
V
REF
------------
×
=
R
DLY
1.96
---------------------------------
t
C
DLY
=
I
R
V
-------------------------------------
1
D
–
(
)
×
f
SW
L
=
L
V
----------------------------------------------------------------
R
1
n
D
×
(
)
–
(
)
×
V
RIPPLE
f
SW
≥
L
1.8V
)
)
≥
594nH
=
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