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參數(shù)資料
| 型號： | FAN5250QSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Mobile Processor Core-Voltage Regulator |
| 中文描述： | SWITCHING CONTROLLER, 690 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | 0.150 INCH, MO-137, QSOP-24 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大小： | 469K |
| 代理商： | FAN5250QSCX |
FAN5250
REV. 1.1.6 3/12/03
15
For the high-side MOSFET, V
DS
= VIN, which can be as
high as 20V in a typical portable application. Q2, however,
switches on or off with its parallel shottky diode conducting,
therefore V
DS
≈
0.5V. Since P
SW
is proportional to V
DS
, Q2's
switching losses are negligible and we can select Q2 based
on R
DS(ON)
only.
Care should also be taken to include the delivery of the
MOSFET's gate power (P
GATE
)
in calculating the power
dissipation required for the FAN5250:
Low-Side Losses
Conduction losses for Q2 are given by:
where R
DS(ON)
is the R
DS(ON)
of the MOSFET at the highest
operating junction temperature and
is the
minimum duty cycle for the converter. Since D
MIN
is 5% for
portable computers, (1-D)
≈
1, further simplifying the calcu-
lation.
The maximum power dissipation (P
D(MAX)
) is a function of
the maximum allowable die temperature of the low-side
MOSFET, the
θ
J-A
, and the maximum allowable ambient
temperature rise:
θ
J-A
, depends primarily on the amount of PCB area that can
be devoted to heat sinking (see FSC app note AN-1029 for
SO-8 MOSFET thermal information).
Table 2. Suggested Component Values
Layout Considerations
Switching converters, even during normal operation, pro-
duce short pulses of current which could cause substantial
ringing and be a source of EMI if layout constrains are not
observed.
There are two sets of critical components in a DC-DC
converter. The switching power components process large
amounts of energy at high rate and are noise generators. The
low power components responsible for bias and feedback
functions are sensitive to noise.
A multi-layer printed circuit board is recommended.
Dedicate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this plane into
smaller islands of common voltage levels.
Notice all the nodes that are subjected to high dV/dt voltage
swing such as SW, HDRV and LDRV, for example. All
surrounding circuitry will tend to couple the signals from
these nodes through stray capacitance. Do not oversize
copper traces connected to these nodes. Do not place traces
connected to the feedback components adjacent to these
traces.
It is not recommended to use High Density Interconnect
Systems, or micro-vias on these signals. The use of blind or
buried vias should be limited to the low current signals only.
The use of normal thermal vias is left to the discretion of the
designer.
Keep the wiring traces from the IC to the MOSFET gate and
source as short as possible and capable of handling peak
currents of 2A. Minimize the area within the gate-source
path to reduce stray inductance and eliminate parasitic
ringing at the gate.
Locate small critical components like the soft-start capacitor
and current sense resistors as close as possible to the respec-
tive pins of the IC.
The FAN5250 utilizes advanced packaging technology that
will have lead pitch of 0.6mm. High performance analog
semiconductors utilizing narrow lead spacing may require
special considerations in PWB design and manufacturing.
It is critical to maintain proper cleanliness of the area sur-
rounding these devices. It is not recommended to use any
type of rosin or acid core solder, or the use of flux in either
the manufacturing or touch up process as these may contrib-
ute to corrosion or enable electromigration and/or eddy
currents near the sensitive low current signals. When
chemicals such as these are used on or near the PWB, it is
suggested that the entire PWB be cleaned and dried com-
pletely before applying power.
Design 1
6 A
1.8μH
Sumida
CEP1231R8MH
4 x 220μF
Sanyo
POSCAP
2R5TPC220M
or
3 x 270μF
Panasonic
EEFUE271R
FDS6612A
Design 2
12 A
1.0μH
Panasonic
ETQP6F1R0BFA
6 x 220μF
Sanyo
POSCAP
2R5TPC220M
or
5 x 270μF
Panasonic
EEFUE271R
FDS6694
Design 3
18 A
0.8μH
Panasonic
ETQP6F0R8BFA
6 x 270μF
Panasonic
EEFUE271R
I
CPU(MAX)
Inductor
Output Caps
High-Side
MOSFETs
Low-Side
MOSFETs
R
for 3%
droop
FDS6694
FDS6690S
2 X FDS6672A
2 X FDS7764A
3.57K
2.8K
3K
P
GATE
Q
G
VDD
F
SW
×
×
=
(16)
(17)
P
COND
1
D
–
(
)
I
OUT
2
×
R
DS ON
)
×
=
D
V
IN
--------------
=
P
D MAX
)
T
------------------------------------------------
T
)
–
J
A
–
=
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