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參數資料
| 型號： | FAN5601MP18X |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩壓器 |
| 英文描述： | Regulated Step-Down Charge Pump DC/DC Converter |
| 中文描述： | SWITCHED CAPACITOR REGULATOR, DSO6 |
| 封裝： | 3 X 3 MM, MO-229WEEA, MLP-6 |
| 文件頁數： | 10/14頁 |
| 文件大小： | 433K |
| 代理商： | FAN5601MP18X |
PRODUCT SPECIFICATION
FAN5601
10
REV. 1.0.4 4/4/05
Detailed Description
The FAN5601 switched capacitor DC/DC converter auto-
matically configures switches to achieve a high efficiency
and provides a regulated output voltage by means of pulse
skipping, pulse frequency modulation (PFM). An internal
soft start circuit prevents excessive inrush current drawn
from the supply. Each switch is split into three segments.
Based on the values of V
IN
,
V
OUT
and I
OUT
, an internal cir-
cuitry determines the number of segments to be used to
reduce current spikes.
Step-Down Charge Pump Operation
When V
IN
≥
2.22
×
V
OUT
, a 2:1 configuration shown in
Fig.1(A) is enabled. The factor 0.9 is used instead of 1 in
order to account for the effect of resistive losses across the
switches and to accommodate hysteresis in the voltage detec-
tor comparator. Two phase non-overlapping clock signals are
generated to drive four switches. When switches 1 and 3 are
ON, switches 2 and 4 are OFF and C
B
is charged. When
switches 2 and 4 are ON, switches 1 and 3 are OFF, charge is
transferred from C
B
to C
OUT
.
When V
IN
<2.22
×
V
OUT
, a 1:1 configuration shown in
Fig. 1(B) is enabled. In the 1:1 configuration switch 3 is
always OFF and the switch 4 is always ON. At 1.6V output
setting the configuration changes from 2:1 to 1:1 at V
IN
=
3.56V. At 1.3V output setting the change occurs at V
IN
=
3.06V
.
Pulse-skipping PFM and Fractional Switch
Operation
When the regulated output voltage reaches its upper limit,
the switches are turned off the output voltage reaches its
lower limit. Considering a step-down 2:1 mode of operation,
1.6V output as an example, when the output reaches about
1.62V(upper limit), the control logic turns off all switches.
Switching stops completely. This is pulse-skipping mode.
Since the supply is isolated from the output, the output volt-
age will drop. Once the output is dropped to about
1.58V(lower limit), the device will return to regular switch-
ing mode with one quarter of each switch turning on first.
Another quarter of each switch will be turned on if V
OUT
cannot reach regulation by the time of arrival of the third
Block Diagram
UVLO
+
-
SHUTDOWN
CONTROL
LOGIC
CONFIGURATION
PULSE_SKIP
SHORT_CKT.
+
-
+
-
+
-
THERMAL
SHUTDOWN
IN
OUT
VrefRAMP
FB
OUTPUT
150mV
1V
0.5* INPUT
VOLTAGE
REF.
SOFT START
Vref RAMP
OSCILLATOR
(2MHz)
C+
C-
ENABLE
VIN
GND.
D
R
I
V
E
R
S
0.25SW1
0.25SW1
0.25SW4
0.25SW4 0.5SW4
0.25SW3
0.25SW3 0.5SW3
0.5SW2
0.25SW2
0.25SW2
0.5SW1
FB
VOUT
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|---|---|
| FAN5602 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Universal (Step-Up/Step-Down) Charge Pump Regulated DC/DC Converter |
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