?2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6921MR Rev. 1.0.4
20
0.3V
I
DET
Auxiliary
Winding
DET
FAN6921
+
V
AUX
-
+
V
DET
-
10
R
A
R
DET
Figure 39. Valley Detection
Figure 40. Measured Waveform of Valley Detection
High / Low Line Over-Power Compensation (DET Pin)
Generally, when the power switch turns off, there is a
delay time from gate signal falling edge to power switch
off. This delay is produced by an internal propagation
delay of the controller and the turn-off delay time of
PWM switch due to gate resistor and gate-source
capacitor C
ISS
of PWM switch. At different AC input
voltage, this delay time produces different maximum
output power under the same PWM current limit level.
Higher input voltage generates higher maximum output
power since applied voltage on primary winding is
higher and causes higher rising slope inductor current. It
results in higher peak inductor current at the same delay
time. Furthermore, under the same output wattage, the
peak switching current at high line is lower than that at
low line. Therefore, to make the maximum output power
close at different input voltages, the controller needs to
regulate V
LIMIT
voltage of the CSPWM pin to control the
PWM switch current.
Referring to Figure 41, during t
ON
time of the PWM
switch, the input voltage is applied to primary winding
and the voltage across on auxiliary winding V
AUX
is
proportional to primary winding voltage. So as the input
voltage increases, the reflected voltage on auxiliary
winding V
AUX
becomes higher as well. FAN6921MR also
clamps the DET pin voltage and flows out a current I
DET
.
Since the current I
DET
is in accordance with V
AUX
voltage, FAN6921MR can depend on this current I
DET
during t
ON
time period to regulate the current limit level
of PWM switch to perform high / low line over-power
compensation.
As the input voltage increases, the reflected voltage on
the auxiliary winding V
AUX
becomes higher as well as
the current I
DET
and the controller regulates the V
LIMIT
to
a lower level.
The R
DET
resistor is connected from auxiliary winding to
the DET pin. Engineers can adjust this R
DET
resistor to
get proper V
LIMIT
voltage to fit power system needs. The
characteristic curve of I
DET
current vs. V
LIMIT
voltage on
CSPWM pin is shown in Figure 42.
(
)
ET
IN
A
P
DET
V    N   N
R
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
(1)
where V
IN
is input voltage; N
A
is turn number of
auxiliary winding; and N
P
is turn number of primary
winding.
Figure 41. Relationship between V
AUX
and V
IN
Figure 42. I
DET
Current vs. V
LIMIT
Voltage
Characteristic Curve
Leading-Edge Blanking (LEB)
When the PFC or PWM switches are turned on, a
voltage spike is induced on the current sense resistor
due to the reciprocal effect by reverse recovery energy
of the output diode and C
OSS
of power MOSFET. To
prevent this spike, a leading-edge blanking time is built-
in   to   FAN6921MR   and   a   small   RC   filter   is   also
recommended between the CSPWM pin and GND (e.g.
100 &, 470 pF).
t
OFF
Start to
detect valley
Idet flow out
from DET pin
Delay time
and then
trigger Gate
signal
Valley
Switching
0V
0V
V
DET
OPWM
V
AUX
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