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參數資料
型號： FAN9612MX
廠商： Fairchild Semiconductor
文件頁數： 25/36頁
文件大?。?/td> 1561K
描述： IC CTLR PFC DUAL BCM 16SOICN
標準包裝： 1
模式： 臨界傳導（BCM）
頻率 - 開關： 16.5kHz ~ 525kHz
電流 - 啟動： 80µA
電源電壓： 9 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應商設備封裝： 16-SOIC N
包裝： 標準包裝
其它名稱： FAN9612MXFSDKR
 
?2008 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN9612 " Rev. 1.1.7
25
Step 12
: Soft-Start Capacitor
(
)
FB2
MAX
OUT,
FB2
FB1
OUT
SS
R
I
0.3
R
R
C
糀
5
C
?/DIV>
?/DIV>
+
?/DIV>
?/DIV>
=
 
(19)
where 5 糀 is the charge current of the soft-start
capacitor and 0.3?/SPAN>I
OUT,MAX
  is the maximum output
current charging the output capacitor of the converter
during the soft-start process. It is imperative to limit the
charge current of the output capacitor to be able to
maintain closed-loop soft-start of the converter. The
0.3 factor used in the C
SS
 equation can prevent output
over voltage at the end of the soft-start period and
provides sufficient margin to supply current to the load
while the output capacitor is charging.
Step 13
: Compensation Components
(
)
FB2
FB1
FB2
2
0
OUT
MAX
OUT,
M
LF
COMP,
R
R
R
f
?/DIV>
2
C
4.1V
I
g
C
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
(20)
where 4.1 V is the control range of the error amplifier
and f
0
 is the desired voltage loop crossover frequency.
It is important to consider that the lowest output ripple
frequency limits the voltage loop crossover frequency.
In PFC applications, that frequency is two times the AC
line frequency. Therefore, the voltage loop bandwidth
(f
0
), is typically in the 5 Hz to 15 Hz range.
To guarantee closed-loop soft-start operation under all
conditions, it is recommended that:
SS
HF
COMP,
C
4
C
?/DIV>
<
 
(21)
This relationship is determined by the ratio between the
maximum output current of the g
M
 error amplifier to the
maximum charge current of the soft-start capacitor.
Observing this correlation between the two capacitor
values ensures that the compensation capacitor voltage
can be adjusted faster than any voltage change taking
place across the soft-start capacitor. Therefore, during
startup the voltage regulation loops response to the
increasing soft-start voltage is not limited by the finite
current capability of the error amplifier.
LF
COMP,
0
COMP
C
f
?/DIV>
2
R
?/DIV>
?/DIV>
?/DIV>
=
1
 
(22)
COMP
HFP
HF
COMP,
R
f
?/DIV>
2
C
?/DIV>
?/DIV>
?/DIV>
=
1
 
(23)
where f
HFP
 is the frequency of a pole implemented in
the error amplifier compensation network against high-
frequency noise in the feedback loop. The pole should
be placed at least a decade higher than f
0
 to ensure
that it does not interfere with the phase margin of the
voltage regulation loop at its crossover frequency. It
should also be sufficiently lower then the switching
frequency of the converter so noise can be effectively
attenuated.
 
The recommended f
HFP
  frequency is around 120 Hz in
PFC applications.
Step 14
: Over-Voltage Protection Setting
(OVP)
OVP
LATCH
OUT,
OV2
P
V
3.5V
R
?/DIV>
=
 
(24)
where 3.5 V is the threshold voltage of the OVP
comparator and P
OVP
  is the total dissipation of the
resistive divider network. Typical P
OVP
 power loss is in
the 50 mW to 100 mW range.
OV2
LATCH
OUT,
OV1
R
1
3.5V
V
R
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>

=
 
(25)
R
OV1
 can be implemented as a series combination of
two or three resistors; depending on safety regulations,
maximum voltage, and or power rating of the selected
resistor type.
Step 15
: Input Line Voltage Sense
Resistors
INSNS
MIN
,
LINE
MAX
,
LINE
2
IN
P
V
2
V
V
925
.
0
R
2
"
"
"
=
 
(26)
where 0.925 V is the brownout protection threshold at
the VIN pin. V
LINE,MIN
  is the minimum input RMS
operating voltage. Its divided down level at the VIN pin
corresponds   to   the   0.925 V   brownout   protection
threshold. V
LINE,MAX
 is the maximum input RMS voltage
anticipated in the design and P
INSNS
 is the total power
dissipation of the R
IN1
  - R
IN2
  divider when the input
voltage equals V
LINE,MAX
. Typical P
INSNS
 power loss is in
the 50 mW to 100 mW range.
IN2
MIN
LINE,
IN1
R
1
0.925V
V
R
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>

?/DIV>
=
2
 
(27)
R
IN1
 can be implemented as a series combination of two
or three resistors; depending on safety regulations,
maximum voltage, and or power rating of the selected
resistor type.
糀
2
V
.
0
R
R
R
V
2
R
IN2
IN1
IN2
ON
LINE,
INHYST
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>

+
?/DIV>
?/DIV>
=
925
 
(28)
where 0.925 V is the threshold voltage of the line
under-voltage lockout comparator and 2 糀 is the sink
current provided at the VIN pin during line under-
voltage   (brownout)   condition.   The   sink   current,
together with the terminating impedance of the VIN pin
determines the hysteresis between the turn-on and
turn-off thresholds.
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