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參數資料
| 型號： | FDT459N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | N-Channel Enhancement Mode Field Effect Transistor |
| 中文描述： | 6.5 A, 30 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁數： | 2/4頁 |
| 文件大小： | 89K |
| 代理商： | FDT459N |
Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
BV
DSS
/
T
J
I
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 μA
I
D
= 250 μA, Referenced to 25
o
C
30
V
Breakdown Voltage Temp. Coefficient
33
mV/
o
C
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
1
μA
T
J
=55°C
10
μA
I
GSSF
I
GSSR
ON CHARACTERISTICS
(Note 2)
Gate - Body Leakage, Forward
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
100
nA
Gate - Body Leakage, Reverse
-100
nA
V
GS(th)
V
GS(th)
/
T
J
R
DS(ON)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 μA
I
D
= 250 μA, Referenced to 25
o
C
1
1.6
2
V
Gate Threshold Voltage Temp.Coefficient
-4.2
mV/
o
C
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 6.5 A
0.031
0.035
T
J
=125°C
0.044
0.06
V
GS
= 4.5 V, I
D
= 5.5 A
V
GS
= 10 V, V
DS
= 5 V
V
DS
= 10 V, I
D
= 6.5 A
0.046
0.055
I
D(ON)
g
FS
DYNAMIC CHARACTERISTICS
On-State Drain Current
20
A
Forward Transconductance
16
S
C
iss
C
oss
C
rss
SWITCHING CHARACTERISTICS
(Note 2)
Input Capacitance
V
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
365
pF
Output Capacitance
210
pF
Reverse Transfer Capacitance
70
pF
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Turn - On Delay Time
V
DD
= 15 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
5.2
11
ns
Turn - On Rise Time
8.2
16
ns
Turn - Off Delay Time
6
12
ns
Turn - Off Fall Time
16
26
ns
Total Gate Charge
V
DS
= 10 V, I
D
= 6.5 A,
V
GS
= 10 V
12
17
nC
Gate-Source Charge
2.2
nC
Gate-Drain Charge
3
nC
I
S
V
SD
Maximum Continuous Drain-Source Diode Forward Current
2.5
A
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 2.5 A
(Note 2)
0.8
1.2
V
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Typical R
θ
JA
using the board layouts shown below on FR-4 PCB in a still air environment:
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%
FDT459NRev.C
a. 42
2oz Cu.
o
C/W when mounted on a 1 in
2
pad of
b. 95
pad of 2oz Cu.
o
C/W when mounted on a 0.066 in
2
c. 110
2
pad of 2oz Cu.
o
C/W when mounted on a 0.00123
in
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