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參數(shù)資料
型號(hào)： FIN12ACMLX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
中文描述： LINE TRANSCEIVER, PQCC32
封裝： 5 X 5 MM, LEAD FREE, MO-220WHHD-4, MLP-32
文件頁(yè)數(shù)： 12/21頁(yè)
文件大小： 1819K
代理商： FIN12ACMLX
Preliminary
www.fairchildsemi.com
12
F
Power Supply Currents
Note 6:
The worst case test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the refer-
ence frequency unless otherwise specified. Maximum power is measured at the maximum V
DD
values. Minimum values are measured at the minimum V
DD
values. Typical values are measured at V
DD
2.5V.
AC Specification: Serializer Timing Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
I
DDA1
Parameter
Test Conditions
Min
Typ
Max
Units
V
DDA
Serializer Static
Supply Current
All DP and Control Inputs at 0V or V
DD
NOCKREF, S2
0, S1
1, DIR
1
TBD
TBD
mA
I
DDA2
V
DDA
Deserializer Static
Supply Current
V
DDS
Serializer Static
Supply Current
V
DDS
Deserializer Static
Supply Current
All DP and Control Inputs at 0V or V
DD
NOCKREF, S2
0, S1
1, DIR
0
All DP and Control Inputs at 0V or V
DD
NOCKREF, S2
0, S1
1, DIR
1
All DP and Control Inputs at 0V or V
DD
NOCKREF, S2
0, S1
1, DIR
0
TBD
TBD
mA
I
DDS1
TBD
TBD
mA
I
DDS2
TBD
TBD
mA
I
DDS
V
DDA
Static
Supply Current
V
DD
Power-Down Supply Current
I
DD_PD
I
DDA
I
DDS
I
DDP
14:1 Dynamic Serializer
Power Supply Current
All DP and Control Inputs at 0V or V
DD
S1
S2
0
S1
S2
0,
TBD
TBD
mA
I
DD_PD
5.0
uA
All Inputs at GND or V
DD
I
DD_SER1
S2
H 5 MHz
S1
L 15 MHz
TBD
TBD
TBD
TBD
mA
CKREF
STROBE
(Note )
I
DD_SER1
I
DDA
I
DDS
I
DDP
DIRI
H
See Figure
S2
H 10 MHz
S1
H 30 MHz
S2
L 30 MHz
TBD
TBD
TBD
TBD
TBD
TBD
S1
H 56 MHz
S2
H 5 MHz
S1
L 15 MHz
TBD
TBD
TBD
TBD
TBD
TBD
I
DD_DES1
14:1 Dynamic Deserializer
Power Supply Current
mA
CKREF
STROBE
(Note )
I
DD_DES1
I
DDA
I
DDS
I
DDP
DIRI
L
See Figure
S2
H 10 MHz
S1
H 30 MHz
S2
L 30 MHz
TBD
TBD
TBD
TBD
TBD
TBD
S1
H 56 MHz
TBD
TBD
TBD
TBD
TBD
TBD
I
DD_SER2
14:1 Dynamic Serializer
Power Supply Current
NOCKREF
STROBE
o
Active
5 MHz
15 MHz
mA
(Note )
I
DD_SER2
I
DDA
I
DDS
I
DDP
CKSI
8X STROBE
DIRI
H
10 MHz
30 MHz
TBD
TBD
TBD
TBD
See Figure
56 MHz
TBD
TBD
Symbol
t
TCP
Parameter
Test Conditions
See Figure
CKREF
STROBE
Min
66.0
33.0
17.8
Typ
Max
166
100
33.0
Units
CKREF Clock Period
(5 MHz - 56MHz)
S2
1
S2
1
S2
0
S1
0
S1
1
S1
1
T
ns
f
REF
CKREF Frequency Relative
to Strobe Frequency
CKREF
Does Not Equal
STROBE
S2
1
S2
1
S2
0
S1
0
S1
1
S1
1
1.1 *
f
ST
15.0
30.0
56.0
MHz
t
TCH
t
TCL
t
CLKT
t
TCH
t
TCL
f
MAX
CKREF Clock High Time
CKREF Clock Low Time
LVCMOS Input Transition Time
TBD
TBD
0.5
0.5
TBD
TBD
TBD
T
T
ns
Figure
STROBE Pulse Width HIGH
STROBE Pulse Width LOW
Maximum
Figure
Figure
5.0
5.0
70.0
ns
ns
S2
0
S1
1
210
Mb/s
Serial Data Rate
REFCK x 14
S2
1
S2
1
S1
0
S1
1
140
420
420
784
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