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參數(shù)資料
| 型號(hào)： | FM24C08UFMT8 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | TSSOP-8 |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大小： | 105K |
| 代理商： | FM24C08UFMT8 |
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FM24C08U/09U Rev. A.3
F
AC Test Conditions
Input Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels
V
CC
x 0.3 to V
CC
x 0.7
Output Load
1 TTL Gate and C
L
= 100 pF
Bus Timing
SCL
SDA
IN
SDA
OUT
tF
tLOW
tHIGH
tR
tLOW
tAA
tDH
tBUF
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
0.9V
CC
0.1V
CC
0.7V
CC
0.3V
CC
Read and Write Cycle Limits (Standard and Low V
CC
Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
Min
400 KHz
Min
Units
Max
Max
f
SCL
SCL Clock Frequency
100
400
KHz
T
I
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
Pulse width)
100
50
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
0.1
0.9
μ
s
t
BUF
Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
μ
s
t
HD:STA
Start Condition Hold Time
4.0
0.6
μ
s
t
LOW
Clock Low Period
4.7
1.5
μ
s
t
HIGH
Clock High Period
4.0
0.6
μ
s
t
SU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
μ
s
t
HD:DAT
Data in Hold Time
0
0
ns
t
SU:DAT
Data in Setup Time
250
100
ns
t
R
SDA and SCL Rise Time
1
0.3
μ
s
t
F
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
0.6
μ
s
t
DH
Data Out Hold Time
300
50
ns
t
Write Cycle Time
4.5V to 5.5V V
CC
2.7V to 4.5V V
CC
(Note 4)
10
15
10
15
ms
Note 4
: The write cycle time (t
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C08U/09U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
AC Testing Input/Output Waveforms
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