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參數資料
| 型號： | FM34W02UM8 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, SO-8 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 95K |
| 代理商： | FM34W02UM8 |
5
www.fairchildsemi.com
FM34W02U Rev. A.1
F
w
Bus Timing
Background Information (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional com-
munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condi-
tion.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROMs, etc., a device type identifier string must
follow the START condition. For EEPROMs, this 4-bit string is
1010. Also refer the
Addressing the WP Register
section.
As shown below, although the EEPROMs on the IIC bus may be
configured in any manner required, the total memory addressed
can not exceed 16K (16,384 bits) on the Standard IIC. EEPROM
memory address programming is controlled by 2 methods:
Hardware configuring the A0, A1, and A2 pins (Device
Address pins) with pull-up or pull-down to V
CC
or V
SS
.
All
unused pins must be grounded
(tied to V
SS
).
Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]
—
[DEVICE ADDRESS]
—
[PAGE BLOCK
ADDRESS]
—
[BYTE ADDRESS]
DEFINITIONS
BYTE
8 bits of data
PAGE
16 sequential addresses (one byte
each) that may be programmed
during a 'Page Write' programming
cycle
PAGE BLOCK
2,048 (2K) bits organized into 16
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) = 2,048
bits
MASTER
Any IIC device CONTROLLING the
transfer of data (such as a micropro-
cessor)
SLAVE
Device being controlled (EEPROMs
are always considered Slaves)
TRANSMITTER
Device currently SENDING data on
the bus (may be either a Master or
Slave).
RECEIVER
Device currently receiving data on the
bus (Master or Slave)
Example of 16K of Memory on 2-Wire Bus
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
SCL
SDA
IN
SDA
OUT
tF
tLOW
tHIGH
tR
tLOW
tAA
tDH
tBUF
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA
SCL
34C02L
VCC
VCC
A0 A1 A2 VSS
24C02
A0 A1 A2 VSS
24C04
A0 A1 A2 VSS
24C08
A0 A1 A2 VSS
VCC
To VCC or VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
VCC
VCC
VCC
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