
Ramtron
FM573/574
27 March 2001
4/10
Functional Description - FM573
The FM573 is an octal transparent latch. The Qn
outputs track the Dn inputs while the Clock C signal
is logic 1. When the C signal goes to logic 0, the Dn
inputs are latched. In this aspect, the FM573 operates
identically to a conventional latch of the same type.
As shown above, it has the same functional truth
table as an ordinary 573-type product. The FM573 is
unique in its behavior during power up and power
down. It also is unique in providing behind the scenes
intelligence to manage the storage of settings.
Each latched state is compared to the stored
nonvolatile state. Comparison is made for each
individual bit. If any bit has changed from its stored
value, the new bit value automatically is written to
the corresponding nonvolatile ferroelectric latch.
Only the changed bits are written. For the transparent
version, unlatched changes on the Qn outputs are not
written to nonvolatile storage. This operation
continues as long as power is within tolerance (above
V
MIN
). The nonvolatile circuit operates entirely in the
background and has no operating impact. When
power is lost, the nonvolatile shadow-latches retain
the final latched state.
On power up, the ferroelectric latches are read. The
outputs of these latches will be placed on the internal
Dn inputs. The power control circuit will then cause
the internal ‘C’ signal to go high. Rather than passing
the inputs signal to the output in transparent fashion,
it will pass the nonvolatile value instead. After
satisfying the minimum high clock-time, the internal
Clock is released and the nonvolatile value is loaded
into the user latch. This entire restore process takes
t
RES
from V
DD
> V
MIN
. After the restored nonvolatile
value is loaded into the user latch, normal operation
begins. The first user write should occur t
PUH
after
VDD
> V
MIN
.
Functional Description - FM574
The FM574 is an octal Dregister. Its behavior is
similar to the FM573 except that Qn outputs do not
change until the rising edge of the Clock. On the
rising edge of the clock signal, the inputs are loaded
and passed to the Qn outputs. In this aspect, the
FM574 operates identically to a conventional latch of
the same type.
The latched state is compared to the stored
nonvolatile state for each bit. If any bit has changed
from its stored value, the new value automatically is
written to the nonvolatile ferroelectric latch. This
operation continues as long as power is within
tolerance. The nonvolatile circuit operates entirely in
the background and has no operating impact. When
power is lost, the nonvolatile shadow-latches retain
the last latched state.
On power up, the ferroelectric latches are read. The
outputs of these latches will be placed on the internal
Dn inputs. The power control circuit will then cause
the internal ‘C’ signal to go high. This rising edge
passes the nonvolatile value instead of the external
input into the user register. The internal Clock will
then be released and the nonvolatile value will be
stored into the user register. This entire restore
process takes t
RES
from VDD
> V
MIN
. After the
restored nonvolatile value is loaded into the user
register, normal operation begins. The first user write
should occur t
PUH
after VDD
> V
MIN
.
Applications
The FM573/FM574 runs at a speed that is
comparable to the industry standard HC family logic.
However, the nonvolatile-write operations, while fast
in nonvolatile memory terms, are slower. Therefore,
the nonvolatile logic runs ‘behind’ the user logic.
Three practical scenarios are identified in this data
sheet. One scenario that is not practical is to have
rapidly changing states, at high speed, continuing
indefinitely. For example, an address latch on a
microprocessor bus is not feasible due to limited
nonvolatile write endurance.
First, a free running clock in the kHz (or less) range
is applied to the FM574. In this application, the
nonvolatile logic can keep pace with state changes
and continue for relatively long periods to
indefinitely depending on the clock frequency. Slow
mechanisms such as relays and valves can be
controlled, and front panel interfaces can be made.
The second scenario is to employ an event driven
clock. The host issues one clock or a high-speed burst
as needed to an FM573 or FM574. In the case of a
high speed burst, the nonvolatile logic may get
behind, but will catch up when the burst is
completed. A special variation is to connect the clock
input to a power-down reset device. This circuit
captures a snapshot of the inputs on power-down. In
this application, care must be taken in the system
design to avoid capturing the inputs on power-up and
thereby losing the old setting. A clock that is either
software generated or controlled by other logic may
be used as well.
The third scenario is to monitor a continuous data
stream and to hold it when an event occurs. This is
analogous to a nonvolatile track-and-hold function.
For this case, the hold signal is applied to an FM573.
Diagrams of these applications are shown below.