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參數資料
| 型號： | FM8P51P |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EPROM/ROM-Based 8-Bit Microcontroller |
| 中文描述： | 存儲器/基于ROM的8位微控制器 |
| 文件頁數： | 29/60頁 |
| 文件大小： | 369K |
| 代理商： | FM8P51P |
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FM8P51
Rev1.2 Mar 15, 2005
P.29/FM8P51
FEELING
TECHNOLOGY
2.7.1 Master Mode
2.7.1.1 Master Mode with SSE Control (SSEMOD = 0)
In this master mode, the data is transmitted/received as soon as the SPI shift register enable bit SSE (SPICON<4>)
bit is setting to “1” by S/W. The data in SPITXB will be loaded into SPISR at the same time and start to shift in/out,
then transmit buffer empty detect bit (TXBF), and interrupt flag bits (SPITXIF, TXBFIF) are set. And then user could
write the next byte data to SPITXB register before the 8-bit data transmission is completed if needed. The SSE bit
will be kept in “1” if the communication is still undergoing. And the SSE bit will be cleared by hardware while the
shifting is completed. Once the 8-bits of data have been received, the data in SPISR will be moved to the SPIRCB
register, then buffer full detect bit (RCBF), interrupt flag bits (SPIRCIF, RCBFIF) are set. And then user could read
out the SPIRCB register before next 8-bit data transmission is completed if needed.
How to transmit/receive data in this master mode:
1. Enable SPI function by setting the SPION (SPICON<6>) bit.
2. Decide the transmission rate and source by programming SPIM2:SPIM0 (SPICON<2:0>) bits.
3. Write the data that you want to transmit to SPITXB register if needed.
4. Set SSE (SPICON<4>) bit to start transmit.
5. When the 8-bit data transmission starts, both of the SPITXIF and TXBFIF interrupt flags will set to 1. Besides,
both of these bits are cleared by software. The TXBF flag also will be set to “1”, cleared by software or by
writting data to SPITXB register.
6. Write next byte data to SPITXB register before this byte transmission being finished if needed.
7. When the 8-bit data transmission is over, the SSE bit will be reset to “0” by hardware. Therefore, if user want to
transmit/receive another 8-bit data, user must set SSE bit to “1” again.
8. When the 8-bit data transmission is completed, both of the SPIRCIF and RCBFIF interrupt flags will set to 1.
Besides, both of these bits are cleared by software. The RCBF flag also will be set to “1”, cleared by software or
by reading out SPIRCB register.
9. Read out the SPIRCB register before next byte transmission being finished if needed.
2.7.1.2 Master Mode without SSE Control (SSEMOD = 1)
In this master mode, the data is transmitted/received as soon as write data to SPITXB register by S/W. The data in
SPITXB will be loaded into SPISR at the same time and start to shift in/out, then transmit buffer empty detect bit
(TXBF), and interrupt flag bits (SPITXIF, TXBFIF) are set. And then user could write the next byte data to SPITXB
register before the 8-bit data transmission is completed if next byte transmission is needed. If the next byte data is
not written into SPITXB, the communication will be stopped after the 8-bit data transmission is completed. Once the
8-bits of data have been received, the data in SPISR will be moved to the SPIRCB register, then buffer full detect bit
(RCBF), interrupt flag bits (SPIRCIF, RCBFIF) are set. And then user could read out the SPIRCB register before
next 8-bit data transmission is completed if needed.
How to transmit/receive data in this master mode:
1. Enable SPI function by setting the SPION (SPICON<6>) bit.
2. Decide the transmission rate and source by programming SPIM2:SPIM0 (SPICON<2:0>) bits.
3. Write the data that you want to transmit to SPITXB register to start transmit.
4. When the 8-bit data transmission starts, both of the SPITXIF and TXBFIF interrupt flags will set to 1. Besides,
both of these bits are cleared by software. The TXBF flag also will be set to “1”, cleared by software or by
writting data to SPITXB register.
5. Write next byte data to SPITXB register before this byte transmission being finished if next byte transmission is
needed.
6. When the 8-bit data transmission is completed, both of the SPIRCIF and RCBFIF interrupt flags will set to 1.
Besides, both of these bits are cleared by software. The RCBF flag also will be set to “1”, cleared by software or
by reading out SPIRCB register.
7. Read out the SPIRCB register before next byte transmission being finished if needed.
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