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參數資料
型號: FM8P54
廠商: Electronic Theatre Controls, Inc.
英文描述: EPROM/ROM-Based 8-Bit Microcontroller Series
中文描述: 存儲器/基于ROM的8位微控制器系列
文件頁數: 15/50頁
文件大小: 368K
代理商: FM8P54
FM8P54/56
Rev1.21 May 31, 2005
P.15/FM8P54/56
FEELING
TECHNOLOGY
2.2 I/O Ports
Port A and port B are bi-directional tri-state I/O ports. Port A is a 4-pin I/O port. Port B is a 8-pin I/O ports. Port C is a
general purpose register.
All I/O pins (IOA<3:0> and IOB<7:0>) have data direction control registers (IOSTA, IOSTB) which can configure
these pins as output or input.
IOB<7:0> have its corresponding pull-high control bits (PHCON register) to enable the weak internal pull-high. The
weak pull-high is automatically turned off when the pin is configured as an output pin.
IOA<3:0> and IOB<3:0> have its corresponding pull-down control bits (PDCON register) to enable the weak internal
pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin.
IOB<7:0> have its corresponding open-drain control bits (ODCON register) to enable the open-drain output when
these pins are configured to be an output pin.
IOA0 and IOA1 are the R-option pins enabled by setting the ROC bit (PCON<4>). When the R-option function is
used, it is recommended that IOA0 and IOA1 are used as output pins, and read the status of IOA0 and IOA1 before
these pins are configured to be an output pin.
IOB<7:0> also provides the input change interrupt/wake-up function. Each pin has its corresponding input change
interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source.
The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input change
interrupt/wake-up function will be disabled by hardware even if it is enabled by software.
FIGURE 2.3: Block Diagram of I/O PINs
IOA3 ~ IOA0 :
D Q
IOST
Latch
> EN
Q
IOST R
Pull-down is not shown in the figure
I/O PIN
D Q
DATA
Latch
> EN Q
Data bus
WR PORT
RD PORT
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